PHP5N40E

Philips Semiconductors Objective specification PowerMOS transistor PHP5N40E GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope featuring high avalanche energy capability, stable blocking voltage, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications. QUICK REFERENCE DATA SYMBOL VDS ID Ptot RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance MAX. 400 6.5 100 1.0 UNIT V A W Ω PINNING - TO220AB PIN 1 2 3 tab gate drain source drain DESCRIPTION PIN CONFIGURATION tab SYMBOL d g 1 23 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDS VDGR ±VGS ID IDM IDR IDRM Ptot Tstg Tj Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (pulse peak value) Source-drain diode current (DC) Source-drain diode current (pulse peak value) Total power dissipation Storage temperature Junction temperature CONDITIONS RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. -55 MAX. 400 400 30 6.5 4.1 26 6.5 26 100 150 150 UNIT V V V A A A A A W ˚C ˚C AVALANCHE LIMITING VALUE SYMBOL PARAMETER WDSS CONDITIONS MIN. MAX. UNIT Drain-source non-repetitive ID = 6.5 A; VDD ≤ 50 V; VGS = 10 V; unclamped inductive ...