Document
Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. The device features very low on-state resistance and has integral zener diodes giving ESD protection. It is intended for use in DC-DC converters and general purpose switching applications.
PHT11N06LT
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Tsp = 25 ˚C Drain current (DC) Tamb = 25 ˚C Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V MAX. 55 10.7 4.9 8.3 150 40 UNIT V A A W ˚C mΩ
PINNING - SOT223
PIN 1 2 3 4 gate drain source drain (tab) DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
d
g s
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 kΩ Tsp = 25 ˚C Tamb = 25 ˚C Tsp = 100 ˚C Tamb = 100 ˚C Tsp = 25 ˚C Tamb = 25 ˚C Tsp = 25 ˚C Tamb = 25 ˚C MIN. - 55 MAX. 55 55 13 10.7 4.9 7.5 3.4 42 19 8.3 1.8 150 UNIT V V V A A A A A A W W ˚C
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model (100 pF, 1.5 kΩ) MIN. MAX. 2 UNIT kV
January 1998
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor Logic level FET
THERMAL RESISTANCES
SYMBOL Rth j-sp Rth j-amb PARAMETER From junction to solder point From junction to ambient CONDITIONS Mounted on any PCB Mounted on PCB of Fig.18 TYP. 12 -
PHT11N06LT
MAX. 15 70
UNIT K/W K/W
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS ±V(BR)GSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current CONDITIONS VGS = 0 V; ID = 0.25 mA Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 150˚C Tj = -55˚C VDS = 55 V; VGS = 0 V; VGS = ±5 V Tj = 150˚C Tj = 150˚C Tj = 150˚C MIN. 55 50 1.0 0.6 10 TYP. 1.5 0.05 0.02 30 MAX. 2.0 2.3 10 100 1 5 40 74 UNIT V V V V V µA µA µA µA V mΩ mΩ
Gate source breakdown voltage IG = ±1 mA Drain-source on-state VGS = 5 V; ID = 5 A resistance
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified SYMBOL gfs Qg(tot) Qgs Qgd Ciss Coss Crss td on tr td off tf PARAMETER Forward transconductance Total gate charge Gate-source charge Gate-drain (Miller) charge Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time CONDITIONS VDS = 25 V; ID = 5 A; Tj = 25˚C ID = 9 A; VDD = 44 V; VGS = 5 V MIN. 11 TYP. 19 17 3.5 10 1050 205 110 17 65 70 70 MAX. 1400 245 150 25 100 105 105 UNIT S nC nC nC pF pF pF ns ns ns ns
VGS.