Document
Philips Semiconductors
Product specification
TrenchMOS™ transistor Standard level FET
GENERAL DESCRIPTION
N-channel enhancement mode standard level field-effect power transistor in a plastic envelope suitable for surface mounting. Using ’trench’ technology, the device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in DC-DC converters and general purpose switching applications.
PHT6N03T
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Tsp = 25 ˚C Drain current (DC) Tamb = 25 ˚C Total power dissipation Junction temperature Drain-source on-state resistance VGS = 10 V MAX. 30 12.8 5.9 8.3 150 30 UNIT V A A W ˚C mΩ
PINNING - SOT223
PIN 1 2 3 4 gate drain source drain (tab) DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
d
g s
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 kΩ Tsp = 25 ˚C Tamb = 25 ˚C Tsp = 100 ˚C Tamb = 100 ˚C Tsp = 25 ˚C Tamb = 25 ˚C Tsp = 25 ˚C Tamb = 25 ˚C MIN. - 55 MAX. 30 30 16 12.8 5.9 9 4.1 51.2 23.6 8.3 1.8 150 UNIT V V V A A A A A A W W ˚C
THERMAL RESISTANCES
SYMBOL Rth j-sp Rth j-amb PARAMETER Thermal resistance junction to solder point Thermal resistance junction to ambient CONDITIONS Mounted on any PCB Mounted on PCB of Fig.19 TYP. 12 MAX. 15 70 UNIT K/W K/W
November 1997
1
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOS™ transistor Standard level FET
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage, all pins CONDITIONS Human body model (100 pF, 1.5 kΩ) MIN. -
PHT6N03T
MAX. 2
UNIT kV
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS ±V(BR)GSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 150˚C Tj = -55˚C VDS = 30 V; VGS = 0 V; VGS = ±10 V; VDS = 0 V Tj = 150˚C Tj = 150˚C Tj = 150˚C MIN. 30 27 2.0 1.0 16 TYP. 3.0 0.05 0.02 24 MAX. 4.0 4.4 10 500 1 20 30 51 UNIT V V V V µA µA µA µA V mΩ mΩ
Gate source breakdown voltage IG = ±1 mA; Drain-source on-state VGS = 10 V; ID = 3.2 A resistance
DYNAMIC CHARACTERISTICS
Tj = 25˚C unless otherwise specified SYMBOL gfs Qg(tot) Qgs Qgd Ciss Coss Crss td on tr td off tf Ld Ld Ls PARAMETER Forward transconductance Total gate charge Gate-source charge Gate-drain (Miller) charge Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 5.9 A ID = 5.9 A; VDD = 24 V; VGS = 10 V MIN. 5 TYP. 10 22.5 4.5 13.5 1500 370 170 16 30 35 25 3.5 4.5 7.5 MAX. 2000 470 250 22 60 50 38 UNIT S nC nC nC pF pF pF ns ns ns ns nH nH nH
VGS = 0 V; VDS = 25 V; f = 1 MHz
VDD = 15 V; ID = 5.9 A; VGS = 10 V; RG = 5 Ω Resistive load Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad
November 1997
2
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOS™ transistor Standard level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 3.2 A; VGS = 0 V IF = 5.9 A; VGS = 0 V IF = 5.9 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 25 V TYP. 0.75 0.85 115 0.3
PHT6N03T
MAX. 6.2 24.8 1.2 -
UNIT A A V ns µC
AVALANCHE LIMITING VALUE
SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 5.9 A; VDD ≤ 25 V; VGS = 10 V; RGS = 50 Ω; Tsp = 25 ˚C MIN. TYP. MAX. 60 UNIT mJ
November 1997
3
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOS™ transistor Standard level FET
PHT6N03T
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
1E+02
Zth j-amb / (K/W)
BUKX83
D= 0.5
0.2 0.1 0.05 0.02
P D tp D= tp T
1E+01
1E+00
1E-01 0
T t
0
20
40
60
80 100 Tmb / C
120
140
1E-02 1E-07
1E-05
1E-03 t/s
1E-01
1E+01
1E+03
Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
ID% Normalised Current Derating
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
ID / A 12 10 8 50 40 30 6 20 10 0 5.5 5 4.5 4 0 2 4 VDS / V 6 8 10 VGS / V = 6.5
120 110 100 90 80 70 60 50 40 30 20 10 0
60
BUK7830-30
0
20
40
60
80 Tmb / C
100
120
140
Fig.2. Norm.