PI6C2502A

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C2502A Phase-Locked Loop Clock Driver Product Features High-Performance Phase-Locked-Loop Clock Distribution for Networking, Synchronous DRAM modules for server/workstation/ PC applications Allows Clock Input to have Spread Spectrum modulation for EMI reduction Zero Input-to-Output delay Low jitter: Cycle-to-Cycle jitter ±75ps max. On-chip series damping resistor at clock output drivers for low noise and EMI reduction Operates at 3.3V VCC Wide range of Clock Frequencies 80 to 134 MHz Package: Plastic 8-pin SOIC Package (W) Product Description The PI6C2502A features a low-skew, low-jitter, phase-locked loop (PLL) clock driver. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. Application If a system designer needs more than 16 outputs with the features just described, using two or more zero-delay buffers such as PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device-to-device skew introduced can significantly reduce the per...