PI6CV855

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory Product Features • PLL clock distribution optimized for SSTL_2 DDR SDRAM applications. • Distributes one differential clock input pair to five differential clock output pairs. • Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 • Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 • External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input. • Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers • Available Package: – Plastic 28-pin TSSOP Product Description PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM applications. This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to five differential pairs of clock outputs (Y[0:4], Y[0:4]) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the Analog Power input (AVDD). When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. ...