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PI74ALVCH1622601 Dataheets PDF



Part Number PI74ALVCH1622601
Manufacturers ETC
Logo ETC
Description 18-Bit Universal Bus Transceiver With 3-State Outputs
Datasheet PI74ALVCH1622601 DatasheetPI74ALVCH1622601 Datasheet (PDF)

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74ALVCH1622601 18-Bit Universal Bus Transceiver With 3-State Outputs Product Features • • • • • • • • • PI74ALVCH1622601is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP.

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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74ALVCH1622601 18-Bit Universal Bus Transceiver With 3-State Outputs Product Features • • • • • • • • • PI74ALVCH1622601is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Inputs/Outputs have equivalent 26Ω series resistors, no external resistors are required. Bus Hold retains last active bus state during 3-state eliminates the need for external pullup resistors Industrial operation at –40°C to +85°C Packages available: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 300 mil wide plastic SSOP (V) Product Description Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. The PI74ALVCH1622601 uses D-type latches and D-type flipflops with 3-state outputs to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by Output Enable (OEAB and OEBA), Latched Enable (LEAB and LEBA), and Clock (CLKAB and CLKBA) inputs. The clock can be controlled by the Clock Enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA. To reduce overshoot and undershoot, the inputs/outputs include 26Ω series resistors. To ensure the high-impedance state during power up or power down, OE should be tied to Vcc through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Logic Block Diagram The PI74ALVCH1622601 has “Bus Hold” which retains the data input’s last state whenever the data input goes to high-impedance preventing “floating” inputs and eliminating the need for pullup/ down resistors. 1 PS8115B 02/03/98 PI74ALVCH1622601 18-BIT UNIVERSAL BUS TRANSCEIVER 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Pin Name CLKEN OE LE CLK Ax Bx GND VCC Description Clock Enable Input (Active LOW) Output Enable Input (Active LOW) Latch Enable (Active HIGH) Clock Input (Active HIGH) Data I/O Data I/O Ground Power Truth Table(1)† CLKENAB X X X H H L L L L Inputs OEAB LEAB H X L H L H L L L L L L L L L L L L CLKAB X X S X X ­ ­ L H A X L H X X L H X X Output B Z L H B0‡ B0‡ L H B0‡ B0§ Product Pin Configuration OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 56-PIN 50 A-56 49 V-56 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Notes: 1. H = High Signal Level L = Low Signal Level Z = High Impedance ↑ = LOW-to-HIGH Transition † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. ‡ Output level before the indicated steady-state input conditions were established. § Output level before the indicated steady-state input conditions were established, provided that CLKAB is LOW before LEAB goes LOW. 2 PS8115B 02/03/98 PI74ALVCH1622601 18-BIT UNIVERSAL BUS TRANSCEIVER 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................................. –65°C to +150°C Ambient Temperature with Power Applied ................. –40°C to +85°C Input Voltage Range, VIN ..................................... –0.5V to VCC +0.5V Output Voltage Range, VOUT ............................... –0.5V to VCC +0.5V DC Input Voltage .......................................................... –0.5V to +5.0V DC Output Current ...................................................................... 100mA Power Dissipation .......................................................................... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating onl.


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