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M40Z300W Dataheets PDF



Part Number M40Z300W
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description NVRAM CONTROLLER for up to EIGHT LPSRAM
Datasheet M40Z300W DatasheetM40Z300W Datasheet (PDF)

M40Z300 M40Z300W NVRAM CONTROLLER for up to EIGHT LPSRAM s s s s s s s s s s CONVERT LOW POWER SRAMs into NVRAMs PRECISION POWER MONITORING and POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION when VCC is OUT-OF-TOLERANCE TWO INPUT DECODER ALLOWS CONTROL for up to 8 SRAMs (with 2 devices active in parallel) CHOICE of SUPPLY VOLTAGES and POWER-FAIL DESELECT VOLTAGES: – M40Z300: VCC = 4.5V to 5.5V THS = VSS 4.5V ≤ VPFD ≤ 4.75V THS = VOUT 4.2V ≤ V PFD ≤ 4.5V – M40Z300W: VCC = 3.0V to 3.6V .

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M40Z300 M40Z300W NVRAM CONTROLLER for up to EIGHT LPSRAM s s s s s s s s s s CONVERT LOW POWER SRAMs into NVRAMs PRECISION POWER MONITORING and POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION when VCC is OUT-OF-TOLERANCE TWO INPUT DECODER ALLOWS CONTROL for up to 8 SRAMs (with 2 devices active in parallel) CHOICE of SUPPLY VOLTAGES and POWER-FAIL DESELECT VOLTAGES: – M40Z300: VCC = 4.5V to 5.5V THS = VSS 4.5V ≤ VPFD ≤ 4.75V THS = VOUT 4.2V ≤ V PFD ≤ 4.5V – M40Z300W: VCC = 3.0V to 3.6V THS = VSS 2.8V ≤ VPFD ≤ 3.0V VCC = 2.7V to 3.3V THS = VOUT 2.5 ≤ VPFD ≤ 2.7V RESET OUTPUT (RST) for POWER ON RESET LESS THAN 12ns CHIP ENABLE ACCESS PROPAGATION DELAY (for 5.0V device) PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT® TOP, or a 16-LEAD SOIC (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY BATTERY LOW PIN (BL) SNAPHAT (SH) Battery 16 28 1 1 SO16 (MQ) SOH28 (MH) Figure 1. Logic Diagram VCC B+(1) THS E B A M40Z300 M40Z300W VOUT BL E1CON E2CON E3CON E4CON RST DESCRIPTION The M40Z300/W NVRAM Controller is a self-contained device which converts a standard low-power SRAM into a non-volatile memory. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. VSS B–(1) NOTE: 1. For 16-pin SOIC package only. AI02242 March 2000 1/16 M40Z300, M40Z300W Figure 2A. SOIC28 Connections Figure 2B. SOIC16 Connections VOUT NC NC RST NC A NC B NC BL NC NC THS VSS 1 28 27 2 26 3 25 4 24 5 23 6 7 M40Z300 22 8 M40Z300W 21 20 9 19 10 18 11 17 12 16 13 15 14 AI02243 VCC E NC NC NC E1CON E2CON NC E3CON NC NC NC E4CON NC VOUT NC RST A B BL THS VSS ( ) = M40Z300W 1 16 15 2 14 3 4 M40Z300 13 5 M40Z300W 12 11 6 7 10 8 9 VCC B+ (B–) E E1CON E2CON E3CON E4CON B– (B+) AI03624 Table 1. Signal Names THS E E1CON-E4CON A, B RST BL VOUT VCC VSS B+ B– NC Threshold Select Input Chip Enable Input Conditioned Chip Enable Output Decoder Inputs Reset Output (Open Drain) Battery Low Output (Open Drain) Supply Voltage Output Supply Voltage Ground Positive Battery Pin Negative Battery Pin Not Connected Internally When an invalid V CC condition occurs, the conditioned chip enable outputs (E1 CON to E4CON ) are forced inactive to write-protect the stored data in the SRAM. During a power failure, the SRAM is switched from the VCC pin to the lithium cell within the SNAPHAT to provide the energy required for data retention. On a subsequent power-up, the SRAM remains write protected until a valid power condition returns. The 28 pin, 330 mil SOIC provides sockets with gold plated contacts for direct connection to a separate SNAPHAT housing containing the battery. The SNAPHAT housing has gold plated pins which mate with the sockets, ensuring reliable connection. The housing is keyed to prevent improper insertion. This unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process which greatly reduces the board manufacturing process complexity of either directly soldering or inserting a battery into a soldered holder. Providing non-volatility becomes a "SNAP". The 16 pin SOIC provides battery pins for an external user supplied battery. 2/16 M40Z300, M40Z300W Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off) Input or Output Voltages Supply Voltage Output Current Power Dissipation M40Z300 M40Z300W SNAPHAT SOIC Value 0 to 70 –40 to 85 –55 to 125 –0.3 to VCC +0.3 –0.3 to 7 –0.3 to 4.6 20 1 Unit °C °C V V mA W Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. OPERATION The M40Z300/W, as shown in Figure 4, can control up to four (eight, if placed in parallel) standard low-power SRAMs. These SRAMs must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (E1CON to E4CON ) output pins follow the chip enable (E) input pin with timing shown in Table 7. An internal switch connects V CC to V OUT. This switch has a voltage drop of less than 0.3V (IOUT1). When V CC degrades during a power failure, E1CON to E4CON are forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance threshold (VPFD). For the M40Z300 the p.


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