M48Z128

M48Z128 M48Z128Y 5.0 V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM Not recommended for new design Features ■ Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited )WRITE cycles t(s■ 10 years of data retention in the absence of cpower du■ Battery internally isolated until power is first roapplied P■ Automatic power-fail chip deselect and WRITE protection lete■ WRITE protect voltages: o(VPFD = power-fail deselect voltage) s– M48Z128: VCC = 4.75 to 5.5 V; b4.5 V ≤ VPFD ≤ 4.75 V O– M48Z128Y: VCC = 4.5 to 5.5 V; ) -4.2 V ≤ VPFD ≤ 4.5 V t(s■ Pin and function compatible with JEDEC standard 128 K x 8 SRAMs uc■ RoHS compliant Obsolete Prod– Lead-free second level interconnect 32 1 PMDIP32 module September 2011 Doc ID 2426 Rev 6 This is information on a product still in production but not recommended for new designs. 1/20 www.st.com 1 Contents Contents M48Z128, M48Z128Y 1 Description . . . . . . ...