MAX5864

19-2915; Rev 1; 10/03 KIT ATION EVALU E L B AVAILA Ultra-Low-Power, High-DynamicPerformance, 22Msps Analog Front End General Description Features o Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs o Ultra-Low Power 42mW at fCLK = 22MHz (Transceiver Mode) 34mW at fCLK = 15.36MHz (Transceiver Mode) Low-Current Idle and Shutdown Modes o Excellent Dynamic Performance 48.5dB SINAD at fIN = 5.5MHz (ADC) 71.7dB SFDR at fOUT = 2.2MHz (DAC) o Excellent Gain/Phase Match ±0.1° Phase, ±0.03dB Gain at fIN = 5.5MHz (ADC) o Internal/External Reference Option o +1.8V to +3.3V Digital Output Level (TTL/CMOS Compatible) o Multiplexed Parallel Digital Input/Output for ADCs/DACs o Miniature 48-Pin Thin QFN Package (7mm ✕ 7mm) o Evaluation Kit Available (Order MAX5865EVKIT) MAX5864 The MAX5864 ultra-low-power, highly integrated analog front end is ideal for portable communication equipment such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5864 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs’ analog I-Q input amplifiers are fully differential and accept 1VP-P full-scale signals. Typical I-Q channel phase matching is ±0.1° and amplitude matching is ±0.03dB. The ADCs feature 48.5dB SINAD and 69dBc spurious-free dynamic range (SFDR) at fIN = 5.5MHz and fCLK = 22Msps. The DACs’ analog I-Q outputs are fully differential with ±400mV full-scale output, and 1.4V common-mode level. Typical I-Q cha...