74LVC1G07

INTEGRATED CIRCUITS DATA SHEET 74LVC1G07 Buffer with open-drain output Product specification Supersedes data of 2000 Nov 22 File under Integrated Circuits, IC24 2001 Apr 06 Philips Semiconductors Product specification Buffer with open-drain output FEATURES Wide supply voltage range from 1.65 to 5.5 V High noise immunity Complies with JEDEC standard: – JESD8-7 (1.65 to 1.95 V) – JESD8-5 (2.3 to 2.7 V) – JESD8B/JESD36 (2.7 to 3.6 V). 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance ≤250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V SOT353 package. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPLZ/tPZL CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. FUNCTION TABLE See note 1. INPUT A L H Note 1. H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. OUTPUT Y L Z PARAMETER propagation delay input A to output Y input capacitance power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 CONDITIONS CL = 50 pF; VCC = 3.3 V DESCRIPTION 74LVC1G07 The 74LVC1G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from eit...