74LVC2GU04

INTEGRATED CIRCUITS DATA SHEET 74LVC2GU04 Dual inverter Product specification Supersedes data of 2004 May 24 2004 Sep 21 Philips Semiconductors Product specification Dual inverter FEATURES Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V. ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay input nA to output nY CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ VCC = 2.5 V; CL = 30 pF; RL = 500 Ω VCC = 2.7 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; CL = 50 pF; RL = 500 Ω VCC = 5.0 V; CL = 50 pF; RL = 500 Ω CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑(CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. input capacitance power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 DESCRIPTION 74LVC2GU04 The 74LVC2GU04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS co...