74LVC574A

74LVC574A Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Rev. 5 — 18 December 2012 Product data sheet 1. General description The 74LVC574A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock (CP) and an Output Enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When OE is LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V or 5 V applications. The 74LVC574A is functionally identical to the 74LVC374A, but has a different pin arrangement. 2. Features and benefits  5 V tolerant inputs for interfacing with 5 V logic  Supply voltage range from 1.2 V to 3.6 V  CMOS low power consumption  Direct interface with TTL levels  High-impedance when VCC = 0 V  8-bit positive edge-triggered register  Independent register and 3-state buffer operation  Flow-through pin-out architecture  Complies with JEDEC standard:  JESD8-7A (1.65 V to 1.95 V)  JESD8-5A (2.3 V to 2....