DatasheetsPDF.com

74LVC86A Dataheets PDF



Part Number 74LVC86A
Manufacturers NXP
Logo NXP
Description Quad 2-input exclusive OR gate
Datasheet 74LVC86A Datasheet74LVC86A Datasheet (PDF)

INTEGRATED CIRCUITS 74LVC86A Quad 2-input exclusive OR gate Product specification Supercedes data of 1997 Aug 11 IC24 Data Handbook 1998 Apr 28 Philips Semiconductors Philips Semiconductors Product specification Quad 2-input exclusive OR gate 74LVC86A FEATURES • Wide supply range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface with TTL levels • 5-volt tolerant inputs, for interfacing with 5-volt l.

  74LVC86A   74LVC86A


Document
INTEGRATED CIRCUITS 74LVC86A Quad 2-input exclusive OR gate Product specification Supercedes data of 1997 Aug 11 IC24 Data Handbook 1998 Apr 28 Philips Semiconductors Philips Semiconductors Product specification Quad 2-input exclusive OR gate 74LVC86A FEATURES • Wide supply range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface with TTL levels • 5-volt tolerant inputs, for interfacing with 5-volt logic QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL tPHL tPLH CI CPD PARAMETER Propagation delay nA, nB to nYn Input capacitance Power dissipation capacitance per gate DESCRIPTION The 74LVC86A is a high-performance, low-power, low-voltage Si-gate CMOS device that is pin and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC86A provides the 2-input EXCLUSIVE-OR function. CONDITIONS CL = 50 pF; VCC = 3.3 V VCC = 3.3 V, VI = GND to VCC 1 TYPICAL 3.0 5.0 28 UNIT ns pF pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi )Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C OUTSIDE NORTH AMERICA 74LVC86A N 74LVC86A D 74LVC86A DB 74LVC86A PW NORTH AMERICA 74LVC86A N 74LVC86A D 74LVC86A DB 74LVC86APW DH PKG. DWG. # SOT27-1 SOT108-1 SOT337-1 SOT402-1 PIN CONFIGURATION 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4B 4A 4Y 3B 3A 3Y LOGIC SYMBOL (IEEE/IEC) 1 2 =1 3 4 5 =1 6 9 10 =1 8 12 =1 SV00481 11 13 PIN DESCRIPTION PIN NUMBER 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A – 4A 1B – 4B 1Y – 4Y GND VCC Data inputs Data outputs Ground (0 V) Positive supply voltage FUNCTION SV00479 1998 Apr 28 2 853-2018 19310 Philips Semiconductors Product specification Quad 2-input exclusive OR gate 74LVC86A LOGIC SYMBOL 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 2Y 3Y 4Y 3 FUNCTION TABLE INPUTS nA 6 8 11 OUTPUTS nB L H L H nY L H H L L L H H NOTES: H = HIGH voltage level L = LOW voltage level SV00480 LOGIC DIAGRAM (ONE GATE) A Y B SV00478 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER DC supply voltage (for max. speed performance) VCC VI VO Tamb tr, tf DC supply voltage (for low-voltage applications) DC Input voltage range DC output voltage range Operating ambient temperature range in free-air Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS MIN 2.7 1.2 0 0 –40 0 0 MAX 3.6 V 3.6 5.5 VCC +85 20 10 V V °C ns/V UNIT ABSOLUTE MAXIMUM RATINGS1 Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage (for max. speed performance) DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 VO = 0 to VCC CONDITIONS RATING –0.5 to +6.5 –50 –0.5 to +5.5 "50 –0.5 to VCC + 0.5 "50 "100 –65 to +150 500 500 UNIT V mA V mA V mA mA °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Apr 28 3 Philips Semiconductors Product specification Quad 2-input exclusive OR gate 74LVC86A DC CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = –12mA VOH O HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC = 3.0V; VI = VIH or VIL; IO = –18mA VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100µA VCC = 3.0V; VI = VIH or VIL; IO = 24mA II ICC ∆ICC Input leakage current Quiescent supply current Additional quiescent su.


74LVC86 74LVC86A 74LVCH162244A


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)