74LVQ174

® 74LVQ174 HEX D-TYPE FLIP FLOP WITH CLEAR s s s s s s s s s s s HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174 IMPROVED LATCH-UP IMMUNITY M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVQ174M 74LVQ174T 3.3V applications. Information signals applied to D inputs are transfered to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independentely of the other inputs . It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. DESCRIPTION The LVQ174 is a low voltage CMOS HEX D-TYPE FLIP FLOP WITH CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/10 74LVQ174 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 5, 7, 10, 1...