74LVTH125

74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs October 1998 Revised January 1999 74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs General Description The LVTH125 contains four independent non-inverting buffers with 3-STATE outputs. These buffers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH125 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. Features s Input and output interface capability to systems at 5V VCC s Bus-Hold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 125 s Latch-up performance exceeds 500 mA Ordering Code: Order Number 74LVTH125M 74LVTH125SJ 74LVTH125MTC Package Number M14A M14D MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Truth Table Pin Descriptions Pin Names An, Bn On Description Inputs 3-STATE Outputs An L L...