74LVTH16500

Preliminary 74LVTH16500 Low Voltage 18-Bit Universal Bus Transceivers May 2000 Revised May 2000 74LVTH16500 Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs (Preliminary) General Description The LVTH16500 is an 18-bit universal bus transceiver combining D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The LVTH16500 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The transceiver is designed for low voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16500 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Features s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 16500 s Latch-up performance exceeds 500 mA Ordering Code: Order Number 74LVTH16500MEA 74LVTH16500MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 56...