74LVX125

74LVX125 — Low Voltage Quad Buffer with 3-STATE Outputs February 2008 74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs Features ■ Input voltage level translation from 5V to 3V ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance General Description The LVX125 contains four independent non-inverting buffers with 3-STATE outputs. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. Ordering Information Order Number 74LVX125M 74LVX125SJ 74LVX125MTC Package Number M14A M14D MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names An OEn On Description Inputs Output Enable Inputs Outputs ©1994 Fairchild Semiconductor Corporation 74LVX125 Rev. 1.4.0 Truth Table Inputs OEn L L H An L H X H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial Output On L H Z www.fairchildsemi.com 74LVX125 — Low Voltage Quad Buffer with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dam...