DatasheetsPDF.com

74LVX161284 Dataheets PDF



Part Number 74LVX161284
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Low Voltage IEEE 161284 Translating Transceiver
Datasheet 74LVX161284 Datasheet74LVX161284 Datasheet (PDF)

74LVX161284 Low Voltage IEEE 161284 Translating Transceiver January 1999 Revised July 2000 74LVX161284 Low Voltage IEEE 161284 Translating Transceiver General Description The LVX161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to t.

  74LVX161284   74LVX161284



Document
74LVX161284 Low Voltage IEEE 161284 Translating Transceiver January 1999 Revised July 2000 74LVX161284 Low Voltage IEEE 161284 Translating Transceiver General Description The LVX161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). Outputs on the cable side can be configured to be either open drain or high drive (± 14 mA) and are connected to a separate power supply pin (VCCcable) to allow these outputs to be driven by a higher supply voltage than the A-side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the VCCcable supply to provide proper termination and pull-ups for open drain mode. Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A1–A8/B1–B8 transceiver pins. Features s Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals s Translation capability allows outputs on the cable side to interface with 5V signals s All inputs have hysteresis to provide noise margin s B and Y output resistance optimized to drive external cable s B and Y outputs in high impedance mode during power down s Inputs and outputs on cable side have internal pull-up resistors s Flow-through pin configuration allows easy interface between the “Peripheral and Host” s Replaces the function of two (2) 74ACT1284 devices Ordering Code Order Number 74LVX161284MEA 74LVX161284MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names HD DIR A1–A8 B1–B8 A9–A13 Y9–Y13 A14–A17 C14–C17 PLHIN PLH HLHIN HLH Description High Drive Enable Input (Active HIGH) Direction Control Input Inputs or Outputs Inputs or Outputs Inputs Outputs Outputs Inputs Peripheral Logic HIGH Input Peripheral Logic HIGH Output Host Logic HIGH Input Host Logic HIGH Output © 2000 Fairchild Semiconductor Corporation DS500202 www.fairchildsemi.com 74LVX161284 Logic Symbol Truth Table Inputs DIR L HD L B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode L H B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 H L A1–A8 Data to B1–B8 (Note 2) A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode H H A1–A8 Data to B1–B8 A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 Note 1: Y9–Y13 Open Drain Outputs Note 2: B1–B8 Open Drain Outputs Outputs Logic Diagram www.fairchildsemi.com 2 74LVX161284 Absolute Maximum Ratings(Note 3) Supply Voltage VCC VCC—Cable VCC—Cable Must Be ≥ VCC Input Voltage (VI)—(Note 4) A1–A13, PLHIN , DIR, HD B1–B8, C14–C17, HLHIN B1–B8, C14–C17, HLHIN Output Voltage (VO) A1–A8, A14–A17, HLH B1–B8, Y9–Y13, PLH B1–B8, Y9–Y13, PLH DC Output Current (IO) A1–A8, HLH B1–B8, Y9–Y13 PLH (Output LOW) PLH (Output HIGH) Input Diode Current (IIK)—(Note 4) DIR, HD, A9–A13, PLH, HLH, C14–C17 Output Diode Current (IOK) A1–A8, A14–A17, HLH B1–B8, Y9–Y13, PLH DC Continuous VCC or Ground Current Storage Temperature ESD (HBM) Last Passing Voltage Recommended Operating Conditions Supply Voltage VCC VCC—Cable DC Input Voltage (VI) Open Drain Voltage (VO) Operating Temperature (TA) 3.0V to 3.6V 3.0V to 5.5V 0V to VCC 0V to 5.5V −0.5V to +4.6V −0.5V to +7.0V −0.5V to VCC + 0.5V −0.5V to +5.5V (DC) −2.0V to +7.0V* *40 ns Transient −40°C to +85°C −0.5V to VCC +0.5V −0.5V to +5.5V (DC) −2.0V to +7.0V* *40 ns Transient ±25 mA ±50 mA 84 mA −50 mA −20 mA ±50 mA −50 mA ±200 mA −65°C to +150 °C 2000V Note 3: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Fairchild does not recommend operation outside the databook specifications. Note 4: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIK VIH Input Clamp Diode Voltage Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage ∆VT Minimum Input Hysteresis VOH Minimum HIGH Level Output Voltage Bn, Yn Bn, Yn PLH An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN An, HLH 3.0–3.6 3.0–3.6 3.0–3.6 3.0–3.6 3.0–3.6 3.0–3.6 3.3 3.3 3.3 3.0 3.0 3.0 3.0 3.15 3.0–5.5 3.0–5.5 3.0–5.5 3.0–5.5 3.0–5.5 3.0–5.5 5.0 5.0 5.0 3.0 3..


74LVX157 74LVX161284 74LVX161284A


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)