Low Voltage Octal Transparent Latch
74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs
June 1993 Revised April 2005
74LVX373 Low Voltage Oc...
Description
74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs
June 1993 Revised April 2005
74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs
General Description
The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.
Features
s Input voltage translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX373M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVX373SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDED J-STD-020B.
Logic Symbols
Pin Descriptions
IEEE/IEC
Pin Names D0–D7 LE OE
Description Data Inputs Latch Enable Input Output Enable Input
O0–O7
3-STATE Latch Outputs
Truth Table
Connection Diagram
I...
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