74VHC125

74VHC125 QUAD BUS BUFFERS (3-STATE) s HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125 s IMPROVED LATCH-UP IMMUNITY s LOW NOISE: VOLP = 0.8V (MAX.) DESCRIPTION The 74VHC125 is an advanced high-speed CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The device requires the 3-STATE control input G to be set high to place the output in to the high impedance state. SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74VHC125MTR 74VHC125TTR Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols November 2004 Rev. 7 1/12 74VHC125 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° 1, 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 7 14 SYMBOL 1G to 4G 1A to 4A 1Y to 4Y GND VCC Table 3: Truth Table NAME AND FUNCTION Output Enable Inputs Data Inputs Data Outputs Ground (0V) Pos...