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MC88914D Dataheets PDF



Part Number MC88914D
Manufacturers Motorola
Logo Motorola
Description LOW SKEW CMOS CLOCK DRIVER WITH RESET
Datasheet MC88914D DatasheetMC88914D Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document from Logic Marketing Low Skew CMOS Clock Driver With Reset The MC88914 is a high–speed, low power, hex divide–by–two D–type flip–flop with matched propagation delays, an internal power–on–reset, and external synchronous reset. With TTL compatible buffered clock and external reset inputs that are common to all flip–flops, the MC88914 is ideal for use in high–frequency systems as a clock driver, providing multiple outputs that are synchr.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document from Logic Marketing Low Skew CMOS Clock Driver With Reset The MC88914 is a high–speed, low power, hex divide–by–two D–type flip–flop with matched propagation delays, an internal power–on–reset, and external synchronous reset. With TTL compatible buffered clock and external reset inputs that are common to all flip–flops, the MC88914 is ideal for use in high–frequency systems as a clock driver, providing multiple outputs that are synchronous. MC88914 • • • • • • LOW SKEW CMOS CLOCK DRIVER WITH RESET Power–on–Reset and External Synchronous Reset TTL Compatible Positive Edge–Triggered Clock Matched Outputs for Synchronous Applications Outputs Source/Sink 24mA Part–to–Part Skew of Less Than 3.0ns Guaranteed Rise and Fall Times for a Given Capacitive Load 14 1 Pinout: 14–Lead Plastic (Top View) VCC 14 GND 13 Q5 12 Q4 11 Q3 10 SR 9 GND 8 N SUFFIX PLASTIC PACKAGE CASE 646–06 14 1 1 VCC 2 GND 3 Q0 4 Q1 5 Q2 6 CLK 7 GND D SUFFIX PLASTIC PACKAGE CASE 751A–03 LOGIC DIAGRAM SR POWER–ON RESET CLK CLK D RST Q CLK D RST Q CLK D RST Q CLK D RST Q CLK D RST Q CLK D RST Q Q0 Q1 Q2 Q3 Q4 Q5 NOTE: This diagram is provided only for understanding of logic operation and should not be used to estimate propagation delays 8/95 © Motorola, Inc. 1995 1 REV 4 MC88914 DC CHARACTERISTICS (unless otherwise specified) Symbol ICC Parameter Maximum Quiescent Supply Current 80 Unit µA Condition VIN = VCC or GND VCC = 5.5V, TA = Worst Case VIN = VCC or GND VCC = 5.5V, TA = 25°C VIN = VCC –2.1V VCC = 5.5V, TA = Worst Case ICC Maximum Quiescent Supply Current 8.0 µA ICCT Maximum Additional ICC/Input 1.5 mA DC CHARACTERISTICS TA = +25°C Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level VCC 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD Maximum Input Maximum ICC/Input Minimum Dynamic Output Current** 5.5 5.5 5.5 0.6 0.001 0.001 Typ 1.5 1.5 1.5 1.5 4.49 5.49 TA = –40 to +85°C Unit V V V V 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 3.76 4.76 0.1 0.1 0.44 0.44 ±0.1 1.5 75 –75 µA mA mA mA V V Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50µA *VIN = VIL or VIH IOH = –24mA –24mA IOUT = 50µA *VIN = VIL or VIH IOH = 24mA 24mA VI = VCC, GND VI = VCC –2.1V VOLD = 1.65V VOHD = 3.85V Guaranteed Max 2.0 2.0 0.8 0.8 4.4 5.4 2.0 2.0 0.8 0.8 4.4 5.4 IOHD 5.5 * All outputs loaded; thresholds on inputs associated with output under test. ** Maximum test duration 20ms, one output at a time. MOTOROLA 2 TIMING SOLUTIONS BR1333 — REV 5 MC88914 AC CHARACTERISTICS (VCC = 5.0V ±10%) TA = 25°C CL = 50 pF Symbol fMAX tPLH, tPHL tPV tPS tOS Parameter Maximum Clock Frequency (50% Duty Cycle) Propagation Delay CLK to Qn, Qn Propagation Delay Variation CLK to Qn, Qn (see Note 1) Propagation Delay Skew (Qn, Qn) |tPHL Actual – tPLH Actual| Output–to–Output Skew (Qn, Qn) |tp Qn – tp Qm| (see Note 2) VCC (V) 5.0 5.0 5.0 5.0 5.0 Min 110 4.0 9.0 3.0 1.0 1.0 Max TA = –40 to +85°C CL = 50 pF Min 110 4.0 11 3.0 1.0 1.0 Max Unit MHz ns ns ns ns trise Rise/Fall Time for Qn, Qn 5.0 3.0 4.0 ns (0.2 x VCC to 0.8 x VCC) tfall 1. For a given set of conditions (i.e., capacitive load, temperature and VCC) the variation from device to device is guaranteed to be less than or equal to the maximum. 2. Where tp Qn and tp Qm are the actual propagation delays (any combination of HIGH or LOW) for any two separate outputs from a given high transition of CLK. AC OPERATING REQUIREMENTS TA = 25°C CL = 50 pF Symbol tW tSU tHD Parameter CLK Pulse Width (HIGH to LOW) Minimum Setup Time, HIGH or LOW SRB to Clock Minimum Hold Time, HIGH or LOW SRB to Clock VCC (V) 5.0 5.0 5.0 Min 3.0 3.5 1.0 Max TA = –40 to +85°C CL = 50 pF Min 3.0 3.5 1.0 Max Unit ns ns ns CAPACITANCE Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Typ 4.5 30 Unit pF pF VCC = 5.0V VCC = 5.0V Condition TIMING SOLUTIONS BR1333 — REV 5 3 MOTOROLA MC88914 OUTLINE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 646–06 ISSUE L 14 8 B 1 7 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0° 10° 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0° 10° 1.01 0.39 A F C N H G D SEATING PLANE L J K M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F DIM A B C D F G H J K L M N –A – 14 8 –B – 1 7 P7 PL 0.25 (0.010) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PR.


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