MC88915TFN133

MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC88915TFN55 MC88915TFN70 MC88915TFN100 MC88915TFN133 MC88915TFN160 Low Skew CMOS PLL Clock Drivers, 3-State 55, 70, 100, 133 and 160MHz Versions The MC88915T Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and workstations. For a 3.3V version, see the MC88LV915T data sheet. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the MC88915T to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple 88915’s can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards (see Figure 7). LOW SKEW CMOS PLL CLOCK DRIVER Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180° phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q” frequency. The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in Figure 5 detail the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of...