Address Inputs (Pins 42-44)
The devices have to receive a correct address before they
will accept data. Three address pins (A2, A1, A0) are used to
define the states of the three programmable bits of
MC14LC5003/MC14LC5004’s 8-bit address.
The address is 0111vwxy where v, w, x represent A2, A1,
and A0 respectively. Where v, w, x=0, then A2, A1, and A0
should be tied to 0 V. Where v, w, x=1, then A2, A1, and A0
should be tied to VDD.
The address pins must be tied to VDD. This deﬁnes the
device as a master.
Note: In applications where the circuit will be isolated from
external manual interference the system designer may take
advantage of the self-programming feature. Upon power-on,
address pins which are left open-circuit will be charged to VDD.
However, care must be taken not to inadvertently discharge
the pins after power-on since the address may then be lost. A
similar feature is also available on the ENB pin.
10 k 100 k 1 M
Figure 6. Oscillator Frequency vs. Load Resistance
Frontplane Drivers (Pins 36-27, 25-22, 19-15, 13-1)
Frontplane driver outputs.
The conﬁguration A0, A1, A2 = 000 should not be used. This
does not give a valid address and is reserved for Motorola’s
use only. All three address pins should never be tied to 0 V
Enable Input (Pin 41)
If the ENB pin is tied to VDD, the MC14LC5003/
MC14LC5004 will always latch the data after 128 bits have
been received. The latched data is multiplexed and fed to the
frontplane drivers for display. If external control of this latching
function is required, then the ENB pin should be held low,
followed by one high pulse on ENB when data display is re-
quired. (This may be useful in a system where one MC145003/
MC145004 is permanently addressed and only the last 128
bits of data sent are required to be latched for display). The
pulse on the ENB pin must occur while DCLK is high.
Data Clock and Data Input (Pins 38, 39)
Address input and data input controls. See Data Input Pro-
tocol sections for relevant option.
Backplane Drivers (Pins 48-45)
Backplane driver outputs.
LCD Driver Supply (Pin 20)
Power supply input for LCD drive outputs. May be used to
supply a temperature-compensated voltage to the LCD drive
section, which can be separate from the logic voltage supply,
Positive Power Supply (Pin 49)
This pin supplies power to the main processor interface and
logic portions of the device. The voltage range is 2.7 to 5.5 V
with respect to the VSS pin.
For optimum performance, VDD should be bypassed to
VSS using a low inductance capacitor mounted very closely
to these pins. Lead length on this capacitor should be mini-
Ground (Pin 21)
Oscillator Pins (Pins 51, 50)
To use the on-board oscillator, an external resistor should
be connected between OSC1 and OSC2. Optionally, the
OSC1 pin may be driven by an externally generated clock
A resistor of 680 k connected between OSC1 and OSC2
pins gives an oscillator frequency of about 30 kHz, giving
approximately 30 Hz as seen at the LCD driver outputs. A
resistor of 200 k gives about 100 kHz, which results in 100Hz
at the driver outputs. LCD manufacturers recommend an LCD
drive frequency of between 30 Hz and 100 Hz. See Figure 6.
DATA INPUT PROTOCOL
Two-wire communication bus DCLK, Din; three-wire com-
munication bus DCLK, Din, ENB.
MC14LC5003 — SERIAL INTERFACE DEVICE (FIGURE 7)
Before communication with an MC14LC5003 can begin, a
start condition must be set up on the bus by the transmitter.
To establish a start condition, the transmitter must pull the
data line low while the clock line is high. The “idle” state for
the clock line and data line is the high state.
After the start condition has been established, an eight-bit
address should be sent by the transmitter. If the address sent
corresponds to the address of the MC14LC5003 then on each
MC14LC5003 • MC14LC5004