MCM6206D

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6206D/D 32K x 8 Bit Fast Static RAM The MCM6206D is fabricated using Motorola’s high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in plastic dual–in–line and plastic small–outline J–leaded packages. Single 5 V ± 10% Power Supply Fully Static — No Clock or Timing Strobes Necessary Fast Access Times: 12, 15, 20, and 25 ns Equal Address and Chip Enable Access Times Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems Low Power Operation: 125 – 140 mA Maximum AC Fully TTL Compatible — Three State Output MCM6206D P PACKAGE 300 MIL PLASTIC CASE 710B–01 J PACKAGE 300 MIL SOJ CASE 810B–03 PIN ASSIGNMENT BLOCK DIAGRAM A1 A3 A4 A6 A7 A8 A9 A11 ROW DECODER MEMORY MATRIX 256 ROWS x 128 x 8 COLUMNS VCC VSS A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ0 DQ7 INPUT DATA CONTROL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 V CC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 . . . VSS COLUMN I/O COLUMN DECODER PIN NAMES A0 – A14 . . . . . . . . . . . . . Address Input DQ0 – DQ7 . . . Data Input/Data Output W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Ou...