MCM67D709

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67D709/D 128K x 9 Bit Synchronous Dual I/O Fast Static RAM The MCM67D709 is a 1,179,648 bit synchronous static random access memory organized as 131,072 words of 9 bits, fabricated using Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates a 128K x 9 SRAM core with advanced peripheral circuitry consisting of address registers, two sets of input data registers and two sets of output latches. This device has increased output drive capability supported by multiple power pins. Asynchronous inputs include the processor output enable (POE) and the system output enable (SOE). The address inputs (A0 – A16) are synchronous and are registered on the falling edge of clock (K). Write enable (W), processor input enable (PIE) and system input enable (SIE) are registered on the rising edge of clock (K). Writes to the RAM are self–timed. All data inputs/outputs, PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, and SDQP have input data registers triggered by the rising edge of the clock. These pins also have three–state output latches which are transparent during the high level of the clock and latched during the low level of the clock. This device has a special feature which allows data to be passed through the RAM between the system and processor ports in either direction. This streaming is accomplished by latching in data from one port and asynchronously output enabling the other port. It is also possible to wri...