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MCM67J618B Dataheets PDF



Part Number MCM67J618B
Manufacturers Motorola
Logo Motorola
Description 64K x 18 Bit BurstRAM Synchronous Fast Static RAM
Datasheet MCM67J618B DatasheetMCM67J618B Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67J618B/D Product Preview MCM67J618B 64K x 18 Bit BurstRAM™ Synchronous Fast Static RAM With Burst Counter and Registered Outputs The MCM67J618B is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS technolo.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67J618B/D Product Preview MCM67J618B 64K x 18 Bit BurstRAM™ Synchronous Fast Static RAM With Burst Counter and Registered Outputs The MCM67J618B is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive registered output drivers onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except output enable (G) are clock (K) controlled through positive–edge–triggered noninverting registers. This device contains output registers for pipeline operations. At the rising edge of K, the RAM provides the output data from the previous cycle. Output enable (G) is asynchronous for maximum system design flexibility. Burst can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the MCM67J618B (burst sequence imitates that of the i486) and controlled by the burst address advance (ADV) input pin. The following pages provide more detailed information on burst controls. Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased flexibility for incoming signals. Dual write enables (LW and UW) are provided to allow individually writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17 (the upper bits). This device is ideally suited for systems that require wide data bus widths and cache memory. See Figure 2 for applications information. • • • • • • • • • • • • Single 5 V ± 5% Power Supply Fast Access Time/Fast Cycle Time = 5 ns/100 MHz, 7 ns/80 MHz Byte Writeable via Dual Write Enables Internal Input Registers (Address, Data, Control) Output Registers for Pipelined Applications Internally Self–Timed Write Cycle ADSP, ADSC, and ADV Burst Control Pins Asynchronous Output Enable Controlled Three–State Outputs Common Data Inputs and Data Outputs 3.3 V I/O Compatible High Board Density 52–Lead PLCC Package ADSP Disabled with Chip Enable (E) — Supports Address Pipelining DQ9 DQ10 VCC VSS DQ11 DQ12 DQ13 DQ14 VSS VCC DQ15 DQ16 DQ17 FN PACKAGE PLASTIC CASE 778–02 PIN NAMES A0 – A15 . . . . . . . . . . . . . . . . Address Inputs K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock ADV . . . . . . . . . . . . Burst Address Advance LW . . . . . . . . . . . . Lower Byte Write Enable UW . . . . . . . . . . . . Upper Byte Write Enable ADSC . . . . . . . . . Controller Address Status ADSP . . . . . . . . . Processor Address Status E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ0 – DQ17 . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground All power supply and ground pins must be connected for proper operation of the device. PIN ASSIGNMENT A6 A7 E UW LW ADSC ADSP ADV K G A8 A9 A10 7 6 5 4 3 2 1 52 51 50 49 48 47 8 46 9 45 10 44 11 43 12 42 13 41 14 40 15 39 16 38 17 37 18 36 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33 A5 A4 A3 A2 A1 A0 VSS VCC A15 A14 A13 A12 A11 DQ8 DQ7 DQ6 VCC VSS DQ5 DQ4 DQ3 DQ2 VSS VCC DQ1 DQ0 BurstRAM is a trademark of Motorola, Inc. i486 and Pentium are trademarks of Intel Corp. This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. 7/96 © Motorola, Inc. 1996 MOTOROLA FAST SRAM MCM67J618B 1 BLOCK DIAGRAM (See Note) ADV BURST LOGIC Q0 K BINARY COUNTER Q1 ADSC CLR A1 A0 A1′ INTERNAL A0′ ADDRESS 16 64K x 18 MEMORY ARRAY ADSP A0 – A15 ADDRESS REGISTER A1 – A0 16 2 A2 – A15 18 9 9 UW LW WRITE REGISTER DATA–IN REGISTERS DATA–OUT REGISTERS 9 9 OUTPUT BUFFER E ENABLE REGISTER G DQ0 – DQ8 DQ9 – DQ17 9 9 NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by negating both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write cycle .


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