74VHC20

® 74VHC20 DUAL 4-INPUT NAND GATE PRELIMINARY DATA s s s s s s s s s HIGH SPEED: tPD = 3.3 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 20 IMPROVED LATCH-UP IMMUNITY M (Micro Package) T (TSSOP Package) ORDER CODES : 74VHC20M 74VHC20T immunity and stable output. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. DESCRIPTION The 74VHC20 is an advanced high-speed CMOS DUAL 4-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provide high noise PIN CONNECTION AND IEC LOGIC SYMBOLS June 1999 1/7 74VHC20 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 9 2, 10 3, 11 4, 12 5, 13 6, 8 7 14 SYMBOL 1A to 2A 1B to 2B N.C. 1C to 2C 1D to 2D 1Y to 2Y GND VCC NAME AND FUNCT ION Data Inputs Data Inputs Not Connected Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage T...