MCM69R736A

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69R736A/D Advance Information 4M Late Write HSTL The MCM69R736A/818A is a 4 megabit synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM69R818A organized as 256K words by 18 bits, and the MCM69R736A organized as 128K words by 36 bits wide are fabricated in Motorola’s high performance silicon gate BiCMOS technology. The differential CK clock inputs control the timing of read/write operations of the RAM. At the rising edge of the CK clock all addresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of the CK clock a cycle after address and control signals. Read data is driven on the rising edge of the CK clock also. The RAM uses HSTL inputs and outputs. The adjustable input trip – point (Vref) and output voltage (VDDQ) gives the system designer greater flexibility in optimizing system performance. The synchronous write and byte enables allow writing to individual bytes or the entire word. The impedance of the output buffers is programmable allowing the outputs to match the impedance of the circuit traces which reduces signal reflections. Byte Write Control Single 3.3 V +10%, – 5% Operation HSTL – I/O (JEDEC Standard JESD8–6 Class I Compatible) HSTL – User Selectable Input ...