74VHC245

® 74VHC245 OCTAL BUS TRANSCEIVER (3-STATE) PRELIMINARY DATA s s s s s s s s s s HIGH SPEED: tPD = 4.0 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON CONTROL INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 245 IMPROVED LATCH-UP IMMUNITY LOW NOISE VOLP = 0.9V (Max.) M (Micro Package) T (TSSOP Package) ORDER CODES : 74VHC245M 74VHC245T used to disable the device so that the busses are effectively isolated. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2kV ESD immunity and transient excess voltage. IT IS PROHIBITED TO APPLY A SIGNAL TO A TERMINAL WHEN IT IS IN OUTPUT MODE AND WHEN A BUS TERMINAL IS FLOATING (HIGH IMPEDANCE STATE) IT IS REQUESTED TO FIX THE INPUT LEVEL BY MEANS OF EXTERNAL PULL DOWN OR PULL UP RESISTOR. DESCRIPTION The 74VHC245 is an advanced high-speed CMOS OCTAL BUS TRANSCEIVER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. This IC is intended for two-way asynchronous communication between data busses; the direction of data trasmission is determined by the level of the DIR input. The enable input G can be PIN CONNECTION AND IEC LOGIC SYMBOLS June 1999 1/8 74VHC245 INPUT EQUIVALENT CIRCUIT PIN DESC...