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SDA9220-5 Dataheets PDF



Part Number SDA9220-5
Manufacturers Siemens
Logo Siemens
Description Memory Sync Controller III
Datasheet SDA9220-5 DatasheetSDA9220-5 Datasheet (PDF)

Memory Sync Controller III SDA 9220-5 Preliminary Data Features Large area flicker elimination through field doubling Additional elimination of interline flicker in field mode Field switching and selection in field mode Noise and cross-color reduction Stills 9-image display, still-in-picture, picture-in-still with different frame versions q Zoom with selection of enlarged picture segment (8 x 12 positions) q Pin-programmable operation without standard conversion q q q q q q MOS IC P-LCC-44-1.

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Memory Sync Controller III SDA 9220-5 Preliminary Data Features Large area flicker elimination through field doubling Additional elimination of interline flicker in field mode Field switching and selection in field mode Noise and cross-color reduction Stills 9-image display, still-in-picture, picture-in-still with different frame versions q Zoom with selection of enlarged picture segment (8 x 12 positions) q Pin-programmable operation without standard conversion q q q q q q MOS IC P-LCC-44-1 Type SDA 9220-5 Functional Description Ordering Code Q67100-H5087 Package P-LCC-44-1 (SMD) The MSC III is a component of the TV-SAM Featurebox and is responsible for driving the picture memory devices (TV-SAMs) and generating sync signals (figure 6). Together with the other devices of the Featurebox it enhances picture quality and offers a number of special operating modes. The MSC III is set via the I2C Bus, it being possible to switch the I2C Bus address by hardware so that implementation of a simple frame Featurebox is possible in conjunction with the signal MUX supplied by the MSC III. Other major output signals of the SDA 9220-5, in addition to the clocks LL3X (13.5 MHz) and LL1.5X (27 MHz), are the memory-driving signals (RA, RB, WT, RE, SCAD, SCA) and the sync signal CSY for the teletext device. The horizontal sync signals (HS2, BLN2) and the vertical sync signals (VS1, VS2) are also generated. Semiconductor Group 117 01.94 SDA 9220-5 Circuit Description The MSC III can be divided into the following function blocks (figure 6): – – – – Sync-signal generator Memory controller Clock generator I2C Bus receiver The sync-signal generator uses signals VS and BLN to produce the horizontal and vertical sync signals BLN2, HS2, VS1 and VS2. It supplies the composite sync signal CSY for the 100-Hz teletext, the control signal MUX for implementing a simple frame Featurebox and the frame signal FRM for inserting a colored frame in multi-picture, still-in-picture and picture-in-still modes. Signal CFH is output to prevent the bottom flutter effect in the video cassette recorder mode. In operation without standard conversion (pin-programmable) signals BLN2, VS2 and FRM are switched from double to single line/field frequency. Outputs CSY and HS2 are not required in this case. The memory controller produces the driving signals (RA, RB, WT, RE) and the addresses (SAR, SAC) for the memory devices (TV-SAMs). In addition, it produces the DREQ pulses used for requesting data from the picture processor during operation with reduced pictures. Two refresh operations are performed in the memory for each TV line. The clock generator consists essentially of a PLL which generates the internal and exported system clocks from input clock LL3 or LL1.5 and synchronizes them with the horizontal blanking signal. The MSC can be set to one of the two input frequencies via input LLSEL. For the possible use of the Featurebox as a channel scanner, the PLL incorporates a crystal-controlled reference clock to ensure an undisturbed clock supply for memory output (stills sequence) during channel-switching phases. All modes (except switching off the standard conversion) are set by appropriate programming of the I2C Bus data bytes. When the operating voltage is switched on, all bits of the associated control registers are set to 0. The address of the I2C Bus is set with signal ADR (24H or 26H). Semiconductor Group 118 SDA 9220-5 Detailed Circuit Description Picture Formats The MSC forms part of a digital television system with line-locked scanning frequency. The nominal word rate is 13.5 MHz for luminance and 3.375 MHz for each of the U and V color components. The active region of a TV line is identified by the high time interval of BLN. It comprises 720 pixels for luminance and 180 pixels each for U and V and is stored in its entirety. In the 50-Hz standard a field consists of 287.5 lines and in the 60-Hz standard of 243.5 lines. 288 lines are stored in the 50-Hz standard (lines 23-310 of the first field, lines 336-623 of the second field) and 243 lines in the 60-Hz standard (lines 17-259 of the first field, lines 280-522 of the second field), (figure 1). In the 9-image mode a field without a frame consists of 208 pixels per line for luminance and 2 x 52 pixels per line for chrominance, with four pixels being lost for luminance and 2 x 1 for chrominance with memory or display frames. The number of lines without a frame is 84 for the 50-Hz standard and 71 for the 60-Hz standard. Two lines less are displayed with a frame (figures 2 and 3). In the picture-in-still (PIS) and still-in-picture (SIP) modes a field without a frame or having a display frame is of the same size as a 9-image window. With the memory frame, however, eight pixels are lost for luminance and 2 x 2 for chrominance (figure 4). For generating the windows in the modes 9-image display, PIS and SIP the picture data are filtered horizontally and vertically in the picture processo.


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