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SDA9253 Dataheets PDF



Part Number SDA9253
Manufacturers Siemens
Logo Siemens
Description 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM)
Datasheet SDA9253 DatasheetSDA9253 Datasheet (PDF)

2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) SDA 9253 Preliminary Data Features q q q q q q q q q q q q q q q q q CMOS IC 212 × 64 × 16 × 12-bit organization Triple port architecture One 16 × 12-bit input shift register Two 16 × 12-bit output shift registers Shift registers independently and simultaneously accessible Continuous data flow even at maximum speed 40-MHz shift rate – 0.96-Gbit/s total data rate All inputs and outputs TTL-compatible Tristate outpu.

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2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) SDA 9253 Preliminary Data Features q q q q q q q q q q q q q q q q q CMOS IC 212 × 64 × 16 × 12-bit organization Triple port architecture One 16 × 12-bit input shift register Two 16 × 12-bit output shift registers Shift registers independently and simultaneously accessible Continuous data flow even at maximum speed 40-MHz shift rate – 0.96-Gbit/s total data rate All inputs and outputs TTL-compatible Tristate outputs Random access of groups of 16 × 12 bits for a wide range of applications Refresh-free operation possible 5 V ± 10 % power supply 0 … 70 °C operating temperature range Low power dissipation: 700 mW active, 28 mW standby Suitable for all common TV standards Allows flicker and noise reduction simultaneously with only one field memory Applications: TV, VCR, image processing, video printers, data compressors, delay lines, time base correctors, HDTV P-MQFP-64-1 Type SDA 9253 Ordering Code Q67101-H5171 Package P-MQFP-64-1 Semiconductor Group 1 1998-01-30 SDA 9253 Functional Description The SDA 9253 is a triple port 2605056 bit dynamic sequential-access memory for high-data-rate video applications. It is organized as 212 rows by 64 columns by 16 arrays by 12 bit to allow for the storage of 12-bit planes of a TV field (NTSC, PAL, SECAM, MAC) in standard or studio quality (13.5-MHz basic sample rate) or 12-bit planes of parts of a HDTV field. The memory is fabricated using the same CMOS technology used for 4-Mbit standard dynamic random access memories. The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit length and 12-bit width, which perform a serial to parallel conversion between the asynchronous input/output data streams and the memory array. The parallel data transfer from the 16 × 12-bit input shift register C to an addressed location of the memory array and from the memory array to one of the 16 × 12-bit output shift registers A or B is controlled by the serial row-(SAR) and column address (SAC) which contains the desired column address and an instruction code (mode bits) for transfer and refresh. Circuit Description Memory Architecture As shown in the block diagram, the TV-SAM comprises 192 memory arrays, which are accessed in parallel. Each memory array has a size of 212 rows by 64 columns. The rows and columns of the 192 arrays can be randomly addressed, reading or writing 16 × 12 bits at a time. To obtain the extremely high data rate at the 12-bit wide data input (SDC) and outputs (SQA, SQB), a parallel to serial conversion is done using shift registers of 16-bit length and 12-bit width. In this way the memory speed is increased by a factor of 16. (This is independent on the number of ports if the total data rate is regarded.) Independent operation of the serial input and the two serial outputs is guaranteed by using three shift registers. The decoupling from the common 16 × 12-bit memory data bus is done by three latches which allow a flexible memory timing and a flying real-time data transfer. A real-time data transfer is necessary to ensure a continuous data flow at the data pins even at maximum clock speed. To save pins without loosing speed, the TV-SAM is addressed serially using a serial 8-bit row address and a serial 8-bit column address which includes two mode control bits. The serial row and column addresses are converted to parallel addresses internally, then latched and fed to the row and column decoders. The internal memory controller is responsible for the timing of the memory read/write access and the refresh operation. Semiconductor Group 2 1998-01-30 SDA 9253 Data Input (SDC, SCB) Data are shifted in through the serial port C (SDC0, …, SDC11) at the rising edge of the shift clock SCB. After 16 clock pulses the data have to be transferred from shift register C to latch C. If more than 16 clock pulses occur before latching the data, only the last sixteen 12-bit data values are accepted. Data Transfer from Shift Register C to Latch C (WT) The contents of the shift register C are transferred to latch C at the falling edge of the write transfer signal WT. If the timing restrictions between WT and the clock SCB are respected, a continuous data flow at input SDC is possible without loosing data. This transfer operation may be asynchronous to all other transfer operations except for a small forbidden window conditioned by the latch C to memory transfer, see diagram 4. Write Transfer from Latch C to Memory (RE) The data of latch C are transferred to the preaddressed location of the memory array at the rising edge of RE, if the mode bits were set to H (M1) and L (M0), see “Addressing and Mode Control.” Addressing and Mode Control (SAR, SAC, SCAD, RE) The serial 8-bit row address SAR and the 8-bit column address/mode code SAC are serially shifted into the TV-SAM (LSB first) at rising edge of the address clock SCAD. After 8 SCAD cycles, the falling e.


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