SDA9254-2

2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter Preliminary Data Features q q q q q q q q q SDA 9254-2 CMOS IC q q q q q q q q q q q q Stores a complete video field (4:1:1) On chip adaptive recursive noise reduction filter (4:1:1) 4 noise reduction classes selectable Special noise reduction mode for 4:2:2 applications 212 × 64 × 16 × 12-bit organization Triple port architecture One 16 × 12-bit input shift register Two 16 × 12-bit output shift registers Shift registers independently and simultaneously accessible (one output shift register is used internally for noise reduction filtering) Continuous data flow even at maximum speed 40-MHz shift rate - 0.96-Gbit/s total data rate All inputs and outputs TTL-compatible Tristate outputs Random access of groups of 16 × 12 bits for a wide range of applications Refresh-free operation possible 5 V ± 10 % power supply 0 … 70 °C operating temperature range Low power dissipation: 700 mW active, 28 mW standby Suitable for all common TV standards Allows flicker and noise reduction simultaneously with only one field memory Applications: TV, VCR, image processing, video printers, data compressors, delay lines, time base correctors, HDTV P-MQFP-64-1 Type SDA 9254-2 Ordering Code on request Package P-MQFP-64-1 Semiconductor Group 1 1998-01-16 SDA 9254-2 Functional Description General The SDA 9254-2 is a combination of the TV-SAM SDA 9253 and an adaptive recursive fil...