74VHCT126A

® 74VHCT126A QUAD BUS BUFFERS (3-STATE) PRELIMINARY DATA s s s s s s s s s s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 126 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (Max.) SOP PACKAGE SOP TSSOP T UBE 74VHCT126AM TSSOP T& R 74VHCT126AMTR 74VHCT126ATTR ORDER CODES DESCRIPTION The 74VHCT126A is an advanced high-speed CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. This device requires the 3-STATE control input G to be set low to place the output into the high impedance state. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS March 2000 1/8 74VHCT126A INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 7 14 SYMBOL 1G to 4G 1A to 4A 1Y to 4Y GND VCC NAME AND FUNCT ION Output Enable Inputs Data Inputs Data Outp...