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M2S28D20ATP-75 Dataheets PDF



Part Number M2S28D20ATP-75
Manufacturers Mitsubishi
Logo Mitsubishi
Description 128M Double Data Rate Synchronous DRAM
Datasheet M2S28D20ATP-75 DatasheetM2S28D20ATP-75 Datasheet (PDF)

DDR SDRAM (Rev.0.1) Jun,'00 Preliminary MITSUBISHI LSIs M2S28D20/ 30/ 40ATP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered .

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