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M2S56D20TP-10 Dataheets PDF



Part Number M2S56D20TP-10
Manufacturers Mitsubishi
Logo Mitsubishi
Description 256M Double Data Rate Synchronous DRAM
Datasheet M2S56D20TP-10 DatasheetM2S56D20TP-10 Datasheet (PDF)

DDR SDRAM (Rev.0.0) Sep.'99 Preliminary MITSUBISHI LSIs M2S56D20/ 30 TP 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION M2S56D20TP is a 4-bank x 16777216-word x 4-bit, M2S56D30TP is a 4-bank x 8388608-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data.

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DDR SDRAM (Rev.0.0) Sep.'99 Preliminary MITSUBISHI LSIs M2S56D20/ 30 TP 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION M2S56D20TP is a 4-bank x 16777216-word x 4-bit, M2S56D30TP is a 4-bank x 8388608-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30 TP achieves very high speed data rate up to 133MHz, and are suitable for main memory in computer systems. FEATURES - Vdd=Vddq=2.5v±0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 1.5/2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Auto precharge / All bank precharge controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8) - SSTL_2 Interface - 400-mil, 66-pin Thin Small Outline Package (TSOP II) - FET switch control(/QFC) - JEDEC standard PIN CONFIGURATION (TOP VIEW) x8 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NU/QFC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 66pin TSOP(II) 7 8 9 10 11 12 13 400mil width x 14 15 875mil length 16 17 18 19 0.65mm 20 Lead Pitch 21 22 23 24 25 ROW 26 A0-12 27 Column 28 A0-9,11(x4) 29 A0-9 (x8) 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS MITSUBISHI ELECTRIC 1 DDR SDRAM (Rev.0.0) Sep.'99 Preliminary MITSUBISHI LSIs M2S56D20/ 30 TP 256M Double Data Rate Synchronous DRAM PIN CONFIGURATION (TOP VIEW) x4 x8 VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NU,/QFC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NU,/QFC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 66pin TSOP(II) 400mil width x 875mil length 0.65mm Lead Pitch ROW A0-12 Column A0-9,11(x4) A0-9 (x8) CLK,/CLK CKE /CS /RAS /CAS /WE DQ0-7 DQS DM /QFC Vref : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Data Strobe : Write Mask : FET Switch Control : Reference Voltage A0-12 BA0,1 Vdd VddQ Vss VssQ : Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output MITSUBISHI ELECTRIC 2 DDR SDRAM (Rev.0.0) Sep.'99 Preliminary MITSUBISHI LSIs M2S56D20/ 30 TP 256M Double Data Rate Synchronous DRAM DQ0 - 7 /QFC DQS BLOCK DIAGRAM DLL I/O Buffer QFC&QS Buffer Memory Array Bank #0 Memory Array Bank #1 Memory Array Bank #2 Memory Array Bank #3 Mode Register Control Circuitry Address Buffer Clock Buffer A0-12 BA0,1 CLK,/CLK CKE Control Signal Buffer /CS /RAS /CAS /WE DM Type Designation Code M 2 S 56 D 3 0 This rule is applied to only Synchronous DRAM family. TP Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0 75: 133MHz@CL=2.5,100MHz@CL=2.0 Package Type TP: TSOP(II) Process Generation Function Reserved for Future Use Organization 2n 2: x4, 3: x8 DDR Synchronous DRAM Density 56: 256M bits Interface V:LVTTL, S:SSTL_3, _2 Memory Style (DRAM) Mitsubishi Main Designation MITSUBISHI ELECTRIC 3 DDR SDRAM (Rev.0.0) Sep.'99 Preliminary MITSUBISHI LSIs M2S56D20/ 30 TP 256M Double Data Rate Synchronous DRAM PIN FUNCTION SYMBOL TYPE DESCRIPTION Clock: CLK and /CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK. Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing). Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refr.


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