M2V56S20AKT

SDRAM (Rev.1.01) Single Data Rate July '01 MITSUBISHI LSIs M2V56S20/ 30/ 40 AKT -5, -6, -7 256M Synchronous DRAM Some of contents are subject to change without notice. DESCRIPTION M2V56S20AKT is a 4-bank x 16777216-word x 4-bit, M2V56S30AKT is a 4-bank x 8388608-word x 8-bit, M2V56S40AKT is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40 AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6), 166MHz(-5) and are suitable for main memory or graphic memory in computer systems. FEATURES - Single 3.3v±0.3V power supply - Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2> - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/full page (programmable) - Burst type- sequential / interleave (programmable) - Random column access - Auto precharge / All bank precharge controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16) - LVTTL Interface - 10.65mm width x 13.1mm length, 64-pin STSOP(II) with 0.4mm lead pitch Max. Frequency @CL2 M2V56S20/30/40 AKT -5 M2V56S20/30/40 AKT -6 M2V56S20/30/40 AKT -7 133 MHz 100MHz 100 MHz Max. Frequency @CL3 166 MHz 133 MHz 100MHz Standard PC133 (CL2...