M368L6423ETN-A2

256MB, 512MB Unbuffered DIMM DDR SDRAM DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 256Mb E-die with 64/72-bit ECC/Non ECC Revision 1.1 August. 2003 Rev. 1.1 August. 2003 256MB, 512MB Unbuffered DIMM Revision History Revision 1.0 (April, 2003) - First release Revision 1.1 (August, 2003) - Corrected typo. DDR SDRAM Rev. 1.1 August. 2003 256MB, 512MB Unbuffered DIMM 184Pin Unbuffered DIMM based on 256Mb E-die (x8,) Ordering Information Part Number M368L3223ETN-C(L)B3/AA/A2/B0 M381L3223ETM-C(L)B3/AA/A2/B0 M368L6423ETN-C(L)B3/AA/A2/B0 M381L6423ETM-C(L)B3/AA/A2/B0 Density 256MB 256MB 512MB 512MB Organization 32M x 64 32M x 72 64M x 64 64M x 72 DDR SDRAM Component Composition 32Mx8 (K4H560838E) * 8EA 32Mx8 (K4H560838E) * 9EA 32Mx8 (K4H560838E) * 16EA 32Mx8 (K4H560838E) * 18EA Height 1,250mil 1,250mil 1,250mil 1,250mil Operating Frequencies B3(DDR333@CL=2.5) Speed @CL2 Speed @CL2.5 CL-tRCD-tRP 133MHz 166MHz 2.5-3-3 AA(DDR266@CL=2) 133MHz 133MHz 2-2-2 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3 Feature Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe(DQS) Differential clock inputs(CK and CK) DLL aligns DQ and DQS transition with CK transition Programmable Read latency 2, 2.5 (clock) Programmable Burst length (2, 4, 8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data ...