M36W108AT

M36W108AT M36W108AB 8 Mbit (1Mb x8, Boot Block) Flash Memory and 1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product PRELIMINARY DATA s SUPPLY VOLTAGE – VCCF = VCCS = 2.7V to 3.6V: for Program, Erase and Read s s ACCESS TIME: 100ns LOW POWER CONSUMPTION – Read: 40mA max. (SRAM chip) – Stand-by: 30µA max. (SRAM chip) – Read: 10mA max. (Flash chip) – Stand-by: 100µA max. (Flash chip) LBGA48 (ZM) 6 x 8 solder balls LGA48 (ZN) 6 x 8 solder lands BGA LGA FLASH MEMORY s 8 Mbit (1Mb x 8) BOOT BLOCK ERASE s s PROGRAMMING TIME: 10µs typical PROGRAM/ERASE CONTROLLER (P/E.C.) – Program Byte-by-Byte – Status Register bits and Ready/Busy Output Figure 1. Logic Diagram s s s SECURITY PROTECTION MEMORY AREA INSTRUCTION ADDRESS CODING: 3 digits MEMORY BLOCKS – Boot Block (Top or Bottom location) – Parameter and Main Blocks 20 A0-A19 W EF G RP E1S E2S M36W108AT M36W108AB RB 8 DQ0-DQ7 VCCF VCCS s s BLOCK, MULTI-BLOCK and CHIP ERASE ERASE SUSPEND and RESUME MODES – Read and Program another Block during Erase Suspend s 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code, M36W108AT: D2h – Device Code, M36W108AB: DCh s SRAM s 1 Mbit (128Kb x 8) s VSS AI02620 POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS LOW VCC DATA RETENTION: 2V 1/36 s March 1999 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M36W108AT, M36W108AB Figure 2. LBGA and LG...