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M378T2953BG0-CC Dataheets PDF



Part Number M378T2953BG0-CC
Manufacturers Samsung
Logo Samsung
Description DDR2 Unbuffered SDRAM MODULE
Datasheet M378T2953BG0-CC DatasheetM378T2953BG0-CC Datasheet (PDF)

256MB,512MB,1GB Unbuffered DIMMs DDR2 SDRAM DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 512Mb B-die 64/72-bit Non-ECC/ECC Revision 1.2 January 2005 Rev. 1.2 Jan. 2005 256MB,512MB,1GB Unbuffered DIMMs DDR2 Unbuffered DIMM Ordering Information Part Number Density Organization Component Composition Number of Rank 1 1 2 1 2 DDR2 SDRAM Height x64 Non ECC M378T3354BG(Z)0-CD5/CC M378T6553BG(Z)0-CD5/CC M378T2953BG(Z)0-CD5/CC M391T6553BG(Z)0-CD5/CC M391T2953BG(Z)0-CD5/CC 256MB 5.

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256MB,512MB,1GB Unbuffered DIMMs DDR2 SDRAM DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 512Mb B-die 64/72-bit Non-ECC/ECC Revision 1.2 January 2005 Rev. 1.2 Jan. 2005 256MB,512MB,1GB Unbuffered DIMMs DDR2 Unbuffered DIMM Ordering Information Part Number Density Organization Component Composition Number of Rank 1 1 2 1 2 DDR2 SDRAM Height x64 Non ECC M378T3354BG(Z)0-CD5/CC M378T6553BG(Z)0-CD5/CC M378T2953BG(Z)0-CD5/CC M391T6553BG(Z)0-CD5/CC M391T2953BG(Z)0-CD5/CC 256MB 512MB 1GB 512MB 1GB 32Mx64 64Mx64 128Mx64 x72 ECC 64Mx72 128Mx72 64Mx8(K4T51083QB)*9 64Mx8(K4T51083QB)*18 30mm 30mm 32Mx16(K4T51163QB)*4 64Mx8(K4T51083QB)*8 64Mx8(K4T51083QB)*16 30mm 30mm 30mm Note: “Z” of Part number stand for Lead-free products. Features • Performance range D5(DDR2-533) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 533 4-4-4 CC(DDR2-400) 400 400 3-3-3 Unit Mbps Mbps Mbps CK • JEDEC standard 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin • 4 Bank • Posted CAS • Programmable CAS Latency: 3, 4, 5 • Programmable Additive Latency: 0, 1 , 2 , 3 and 4 • Write Latency(WL) = Read Latency(RL) -1 • Burst Length: 4 , 8(Interleave/nibble sequential) • Programmable Sequential / Interleave Burst Mode • Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) • Off-Chip Driver(OCD) Impedance Adjustment • On Die Termination • Average Refesh Period 7.8us at lower then TCASE 85×C, 3.9us at 85×C < TCASE < 95 ×C • Serial presence detect with EEPROM • DDR2 SDRAM Package: 60ball FBGA - 64Mx8, 84ball FBGA - 32Mx16 • All of Lead-free products are compliant for RoHS Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. Rev. 1.2 Jan. 2005 256MB,512MB,1GB Unbuffered DIMMs Address Configuration Organization 64Mx8(512Mb) based Module 32Mx16(512Mb) based Module DDR2 SDRAM Bank Address BA0-BA1 BA0-BA1 Row Address A0-A13 A0-A12 Column Address A0-A9 A0-A9 Auto Precharge A10 A10 x64 DIMM Pin Configurations (Front side/Back side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Front VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS NC NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Back VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS CK1 CK1 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Front DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS NC NC VSS NC NC VSS NC NC VSS VDDQ CKE0 VDD NC NC VDDQ A11 A7 VDD A5 Pin 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Back VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS NC NC VSS NC NC VSS NC NC VSS VDDQ CKE1 VDD NC NC VDDQ A12 A9 VDD A8 A6 Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Front A4 VDDQ A2 VDD Pin 181 182 183 184 KEY 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 Back VDDQ A3 A1 VDD CK0 CK0 VDD A0 VDD BA1 VDDQ RAS S0 VDDQ ODT0 A131 VDD VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS Pin 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Front VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC, TEST2 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Back DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 CK2 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA0 SA1 VSS VSS VDD NC VDD A10/AP BA0 VDDQ WE CAS VDDQ S1 ODT1 VDDQ VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 NC = No Connect, RFU = Reserved for Future Use 1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM. 2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.) SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 1.2 Jan. 2005 256MB,512MB,1GB Unbuffered DIMMs x72 DIMM Pin Configurations (Front side/Back side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DDR2 SDRAM Front A4 VDDQ A2 VDD KEY VSS VSS VDD NC VDD A10/AP BA0 VDDQ WE CAS VDDQ S1 ODT1 VDDQ VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 Front VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS NC NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Back VSS DQ4 DQ5.


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