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Shift Register. 74HC595 Datasheet

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Shift Register. 74HC595 Datasheet






74HC595 Register. Datasheet pdf. Equivalent




74HC595 Register. Datasheet pdf. Equivalent





Part

74HC595

Description

8-Bit Serial-Input/Serial or Parallel-Output Shift Register



Feature


74HC595 8−Bit Serial−Input/Serial o r Parallel−Output Shift Register with Latched 3−State Outputs High−Perfo rmance Silicon−Gate CMOS The 74HC595 consists of an 8−bit shift register a nd an 8−bit D−type latch with three −state parallel outputs. The shift re gister accepts serial data and provides a serial output. The shift register al so provides parallel data to the 8−bit.
Manufacture

ON Semiconductor

Datasheet
Download 74HC595 Datasheet


ON Semiconductor 74HC595

74HC595; latch. The shift register and latch hav e independent clock inputs. This device also has an asynchronous reset for the shift register. The HC595 directly int erfaces with the SPI serial data port o n CMOS MPUs and MCUs. Features • Outp ut Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS, NM OS, and TTL • Operating Voltage Range : 2.0 to 6.0 V • Low Inp.


ON Semiconductor 74HC595

ut Current: 1.0 mA • High Noise Immuni ty Characteristic of CMOS Devices • I n Compliance with the Requirements Defi ned by JEDEC Standard No. 7A • ESD Pe rformance: HBM > 2000 V; Machine Model > 200 V • Chip Complexity: 328 FETs o r 82 Equivalent Gates • Improvements over HC595 − Improved Propagation Del ays − 50% Lower Quiescent Power − I mproved Input Noise and Latchup Im.


ON Semiconductor 74HC595

munity • These are Pb−Free Devices 16 1 16 1 http://onsemi.com MARKING D IAGRAMS 16 SOIC−16 D SUFFIX CASE 75 1B HC595G AWLYWW 1 TSSOP−16 DT SUF FIX CASE 948F 16 HC 595 ALYW G G 1 HC 595 = Device Code A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb−Free Package ( Note: Microdot may be in either locatio n) ORDERING INFORMATION See .

Part

74HC595

Description

8-Bit Serial-Input/Serial or Parallel-Output Shift Register



Feature


74HC595 8−Bit Serial−Input/Serial o r Parallel−Output Shift Register with Latched 3−State Outputs High−Perfo rmance Silicon−Gate CMOS The 74HC595 consists of an 8−bit shift register a nd an 8−bit D−type latch with three −state parallel outputs. The shift re gister accepts serial data and provides a serial output. The shift register al so provides parallel data to the 8−bit.
Manufacture

ON Semiconductor

Datasheet
Download 74HC595 Datasheet




 74HC595
74HC595
8−Bit Serial−Input/Serial or
Parallel−Output Shift
Register with Latched
3−State Outputs
HighPerformance SiliconGate CMOS
The 74HC595 consists of an 8bit shift register and an 8bit Dtype
latch with threestate parallel outputs. The shift register accepts serial
data and provides a serial output. The shift register also provides
parallel data to the 8bit latch. The shift register and latch have
independent clock inputs. This device also has an asynchronous reset
for the shift register.
The HC595 directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
Features
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC
Standard No. 7A
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 328 FETs or 82 Equivalent Gates
Improvements over HC595
Improved Propagation Delays
50% Lower Quiescent Power
Improved Input Noise and Latchup Immunity
These are PbFree Devices
16
1
16
1
http://onsemi.com
MARKING
DIAGRAMS
16
SOIC16
D SUFFIX
CASE 751B
HC595G
AWLYWW
1
TSSOP16
DT SUFFIX
CASE 948F
16
HC
595
ALYW G
G
1
HC595 = Device Code
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 Rev. 1
1
Publication Order Number:
74HC595/D




 74HC595
PIN ASSIGNMENT
QB 1
QC 2
QD 3
QE 4
QF 5
QG 6
QH 7
GND 8
16 VCC
15 QA
14 A
13 OUTPUT ENABLE
12 LATCH CLOCK
11 SHIFT CLOCK
10 RESET
9 SQH
74HC595
SERIAL
DATA
INPUT
A 14
LOGIC DIAGRAM
SHIFT
REGISTER
LATCH
SHIFT 11
CLOCK
RESET 10
LATCH 12
CLOCK
OUTPUT 13
ENABLE
15 QA
1 QB
2 QC
3 QD
4 QE
5 QF
6 QG
7 QH
PARALLEL
DATA
OUTPUTS
9 SQH
SERIAL
DATA
OUTPUT
VCC = PIN 16
GND = PIN 8
ORDERING INFORMATION
Device
Package
Shipping
74HC595DR2G
SOIC16
(PbFree)
2500 Tape & Reel
74HC595DTR2G
TSSOP16*
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.
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2




 74HC595
74HC595
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VCC DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
Vin DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5 V
Vout DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5 V
Iin DC Input Current, per Pin
±20 mA
Iout DC Output Current, per Pin
±35 mA
ICC DC Supply Current, VCC and GND Pins
±75 mA
PD Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
mW
Tstg Storage Temperature
– 65 to + 150
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
TL Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
260
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
TA Operating Temperature, All Package Types
tr, tf Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
2.0
0
– 55
0
0
0
Max
6.0
VCC
Unit
V
V
+ 125
1000
500
400
_C
ns
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3



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