M74HC107

M74HC107 DUAL J-K FLIP FLOP WITH CLEAR s HIGH SPEED : fMAX = 80MHz (TYP.) at VCC = 6V s LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: )VNIH = VNIL = 28 % VCC (MIN.) t(ss SYMMETRICAL OUTPUT IMPEDANCE: c|IOH| = IOL = 4mA (MIN) us BALANCED PROPAGATION DELAYS: dtPLH ≅ tPHL ros WIDE OPERATING VOLTAGE RANGE: PVCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH te74 SERIES 107 oleDESCRIPTION bsThe M74HC107 is an high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate OC2MOS technology. These flip-flop are edge -sensitive to the clock input and change state on t(s)the negative going transition of the clock pulse. Each one has independent J, K, CLOCK, and DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC107B1R M74HC107M1R T&R M74HC107RM13TR M74HC107TTR CLEAR input and Q and Q outputs. CLEAR is independent of the clock and accomplished by a logic low on the input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. Obsolete ProducPIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 M74HC107 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 8, 4, 11 1J, 2J, 1K, Synchronous Inputs; 2K Flip-Flop 1 And 2 2, 6 1Q, 2Q Complement Flip-Flop Outputs 3, 5 1Q, 2Q True Flip-Flop Outputs 12, 9 1CK, 2CK Clock Input 13, 10 1CLR, 2CLR Asynchronous Reset Inputs 7 GND Ground (0V) t(s)TRUTH TABLE roducCLR PL teH leH soH bH OH ) -X :...