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M74HC113 Dataheets PDF



Part Number M74HC113
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description DUAL J-K FLIP FLOP WITH PRESET
Datasheet M74HC113 DatasheetM74HC113 Datasheet (PDF)

M54HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET . . . . . . . . HIGH SPEED fMAX = 71 MHz (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA at TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS113 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Pac.

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M54HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET . . . . . . . . HIGH SPEED fMAX = 71 MHz (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA at TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS113 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC113F1R M74HC113M1R M74HC113B1R M74HC113C1R DESCRIPTION The M54/74HC113 is a high speed CMOS DUAL JK FLIP FLOP WITH PRESET fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This circuit offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will function as shown in the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection October 1992 1/11 M54/M74HC113 TRUTH TABLE INPUTS PR L H H H H H X: Don’t Care OUTPUTS K X L H L H X CK X Q H Qn L H Qn Qn Q L Qn H L Qn Qn J X L L H H X FUNCTION PRESET NO CHANGE TOGGLE NO CHANGE LOGIC DIAGRAM 2/11 M54/M74HC113 PIN DESCRIPTION PIN No 1, 13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 SYMBOL 1CK, 2CK 1K, 2K 1J, 2J 1PR, 2PR 1Q, 2Q 1Q, 2Q GND V CC NAME AND FUNCTION Clock Input (HIGH to LOW edge triggered) Data Inputs: Flip-Flop 1 and 2 Data Inputs: Flip-Flop 1 and 2 Set Inputs True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOL ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mW o o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. (*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature: M54HC Series M74HC Series Input Rise and Fall Time Value 2 to 6 0 to VCC 0 to VCC -55 to +125 -40 to +85 0 to 1000 0 to 500 0 to 400 Unit V V V C o C ns o VCC = 2 V VCC = 4.5 V VCC = 6 V 3/11 M54/M74HC113 DC SPECIFICATIONS Test Conditions Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 V OH High Level Output Voltage 2.0 4.5 6.0 4.5 VOL Low Level Output Voltage 6.0 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 VI = IO=-20 µA VIH or V IL IO=-4.0 mA IO=-5.2 mA VI = IO= 20 µA VIH or V IL IO= 4.0 mA IO= 5.2 mA VI = VCC or GND VI = VCC or GND 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 ±0.1 2 TA = 25 C 54HC and 74HC Min. Typ. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 ±1 20 o Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 ±1 40 µA µA V V 1.5 3.15 4.2 0.5 1.35 1.8 V V Unit VIH High Level Input Voltage Low Level Input Voltage V IL 4/11 M54/M74HC113 AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns) Test Conditions Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 tREM Minimum Removal Time (PRESET) Input Capacitance Power Dissipation Capacitance 2.0 4.5 6.0 5 37 8 40 47 TA = 25 C 54HC and 74HC Min. Typ. Max. 30 8 7 46 16 12 48 16 13 16 63 79 16 4 3 16 4 3 16 4 3 75 15 13 75 15 13 50 10 9 0 0 0 5 5 5 10 75 15 13 125 25 21 125 25 21 6.4 32 38 95 19 16 95 19 16 65 13 11 0 0 0 5 5 5 10 o Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 95 19 16 155 31 26 155 31 26 5.4 27 32 110 22 19 110 22 19 75 15 13 0 0 0 5 5 5 1 0 pF pF ns ns ns ns MHz 110 22 19 190 38 32 190 38 32 ns ns ns Unit tTLH tTHL tPLH tPHL tPLH tPHL fMAX Output Transition Time Propagation Delay Time (CK - Q, Q) Propagation Delay Time (PRESET - Q, Q) Maximum Clock Frequency Minimum Pulse Width (CLOCK) Minimum Pulse Width (PRESET) Minimum Set-up Time Minimum Hold Time tW(H) tW(L) tW(L) ts th ns CIN CPD (*) (*) CPD is defined.


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