M74HC279

M54HC279 M74HC279 QUAD S - R LATCH . . . . . . . . HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS279 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC279F1R M74HC279M1R M74HC279B1R M74HC279C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC279 is a high speed CMOS QUAD S - R LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT NC = No Internal Connection March 1993 1/10 M54/M74HC279 PIN DESCRIPTION PIN No SYMBOL 1, 5, 10. 14 1R to 4R 2, 3, 6, 11, 1S1, 1S2, 2S, 12, 15 3S1, 3S2, 4S 4, 7, 9, 13 1Q to 4Q 8 GND 16 V CC NAME AND FUNCTION Reset Inputs (Active LOW) Set Inputs (Active LOW) Outputs Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOL TRUTH TABLE S # H L H L R H H L L Q Q0 H L H NOTE: Q0 = THE LEVEL OF Q BEFORE THE INDICRTED INPUT CONDITION WAS ESTABLISHED. # FOR LATCHES WITH DOUBLE S INPUT: H = BOTH S INPUTS HIGH L = ONE OF BOTH INPUTS LOW LOGIC D...