M74HC4515

M74HC4514 4 TO 16 LINE DECODER/LATCH s s s s s s s HIGH SPEED: tPD= 20 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4514 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC4514B1R M74HC4514M1R T&R M74HC4514RM13TR M74HC4514TTR DESCRIPTION The M74HC4514 is an high speed CMOS 4 LINE TO 16 LINE SEGMENT DECODER WITH LATCHED INPUTS fabricated with silicon gate C2MOS technology. A binary code stored in the four input latches (A to D) provides a high level at the selected one of sixteen outputs excluding the other fifteen outputs, when the inhibit input (INHIBIT) is held low. When the inhibit input (INHIBIT) is held high, all outputs are kept low level, while the latch function is available. The data applied to the data inputs are transferred to the Q outputs of latches when the strobe input is held high. When the strobe input is taken low, the information data applied to the data input at a time is retained at the output of the latches. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS April 2003 1/12 M74HC4514 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 3, 21, 22 11, 9, 10, 8, 7, 6, 5, 4...