M74HC597

M54HC597 M74HC597 8 BIT LATCH/SHIFT REGISTER . . . . . . . . HIGH SPEED fMAX = 60 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS597 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC597F1R M74HC597M1R M74HC597B1R M74HC597C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC597 is a high speed CMOS 8-BIT LATCH/SHIFT REGISTER fabricated in silicon gate 2 C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This devices comes in a 16-pin package and consist of an 8-bit storage latch feeding a parallel-in, serialout 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. All inputs are equipped with protection circuits against static discharge and transient voltage excess. October 1992 NC = No Internal Connection 1/13 M54/M74HC597 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS SI X X L H X X X X: DON’T CARE SCK X X SCLR L H H H H SLOAD H L H H H X X RCK X X X X X OUTPUT S.R. IS CLEARED TO ”L” INPTU REGISTER DATA IS STORED...