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M74HC623 Dataheets PDF



Part Number M74HC623
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description OCTAL BUS TRANSCEIVER
Datasheet M74HC623 DatasheetM74HC623 Datasheet (PDF)

M54/74HC620 M54/74HC623 OCTAL BUS TRANSCEIVER HC620 3 STATE INVERTING HC623 3 STATE NON INVERTING . . . . . . . . HIGH SPEED tPD = 10 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH LS620/623 B1R (Pl.

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M54/74HC620 M54/74HC623 OCTAL BUS TRANSCEIVER HC620 3 STATE INVERTING HC623 3 STATE NON INVERTING . . . . . . . . HIGH SPEED tPD = 10 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH LS620/623 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HCXXXF1R M74HCXXXM1R M74HCXXXB1R M74HCXXXC1R DESCRIPTION The M54/74HC620/623 are high speed CMOS OCTAL BUS TRANSCEIVERS fabricated in silicon 2 gate C MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation allows maximum flexibility in timing. These devices allow data transmission from the A bus to B bus or from the B to the A bus depending upon the logic levels at the enable inputs (GBA and GAB). The enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of GBA and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The 8bit codes appearing on the two sets of buses will be identical for the ’HC623 or complementary for the ’HC620. All inputs are equipped with protection circuits against static discharge and transient excess voltage. October 1992 PIN CONNECTIONS (top view) NC = No Internal Connection 1/11 M54/M74HC620/623 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS GAB L H L H GBA L H H L A Bus Output Input FUNCTION B Bus Input Output HC620 A=B B=A Z Z OUTPUS HC623 A=B B=A Z Z High Impedance High Impedance LOGIC DIAGRAM 2/11 M54/M74HC620/623 PIN DESCRIPTION PIN No 1, 19 2, 3, 4, 5, 6, 7, 8, 9 11, 12, 13, 14, 15, 16, 17, 18 10 20 SYMBOL GBA , GAB A1 to A8 B1 to B8 GND VCC NAME AND FUNCTION Direction Controls Data Inputs/Outputs Data Inputs/Outputs Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOLS HC620 HC623 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 35 ± 70 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mW o C o C Absolute Maximum Ratings are those values beyond .


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