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M74HC646 Dataheets PDF



Part Number M74HC646
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description HC648 OCTAL BUS TRANSCEIVER/REGISTER
Datasheet M74HC646 DatasheetM74HC646 Datasheet (PDF)

M74HC646 M74HC648 HC646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE) HC648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.) . . . . . . . . HIGH SPEED fMAX = 73 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH= IOL = 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WI.

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M74HC646 M74HC648 HC646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE) HC648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.) . . . . . . . . HIGH SPEED fMAX = 73 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH= IOL = 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS646/648 B1R (Plastic Package) M1R (Micro Package) ORDER CODES : M74HCXXXM1R M74HCXXXB1R DESCRIPTION The M74HC646/648 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS, (32 STATE) fabricated in silicon gate C MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices consist of bus transceiver circuits with 3-state output, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers on the low-to-high transition of the appropriate clock pin (Clock AB - or Clock BA). Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (Select AB select BA) can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when enable G is active (low). In the isolation mode (enable G high), ”A” data may be stored in one register and/or ”B” data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. All inputs are equipped with protection circuits PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIVALENT CIRCUIT GAB, GAB, CAB, SAB, SBA, CBA A, B October 1993 1/12 M74HC646/648 LOGIC DIAGRAM (HC648) Note : In case of M54/74HC646 output inverter marked * at A bus and B bus are eliminated. TIMING CHART 2/12 M74HC646/648 TRUTH TABLE HC646 (The truth table for HC648 is the same as this, but with the outputs inverted) G DIR CAB CBA SAB SBA X H X X X X X X A INPUTS Z INPUTS B INPUTS Z INPUTS FUNCTION Both the A bus and the B bus are inputs The output functions of the A and B bus are disabled Both the A and B bus are used for inputs to the internal flip-flops. Data at the bus will be stored on low to high transition of the clock inputs The A bus are inputs and the B bus are outputs The data at the A bus are displayed at the B bus The data at the A bus are displayed at the B bus. The data of the A bus are stored to the internal flip-flop on low to high transition of th clock pulse. The data stored to the internal flip-flop are dispayed at the B bus The data at the A bus are store.


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