HEX D-TYPE FLIP-FLOP
M74HCT174
HEX D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED :
fMAX = 56MHz (TYP.) at VCC = 4.5V
s LOW POWER DISSIPATION:
...
Description
M74HCT174
HEX D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED :
fMAX = 56MHz (TYP.) at VCC = 4.5V
s LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
s COMPATIBLE WITH TTL OUTPUTS :
VIH = 2V (MIN.) VIL = 0.8V (MAX) s SYMMETRICAL OUTPUT IMPEDANCE:
DIP
SOP
TSSOP
|IOH| = IOL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
t(s)s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174
ducDESCRIPTION roThe M74HCT174 is an high speed CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR fabricated with
Psilicon gate C2MOS technology. teInformation signals applied to D inputs are letransferred to the Q output on the positive going oedge of the CLOCK (CK) pulse. When the CLEAR
ORDER CODES
PACKAGE
TUBE
T&R
DIP SOP TSSOP
M74HCT174B1R M74HCT174M1R M74HCT174RM13TR
M74HCT174TTR
(CLR) input is held low, the Q outputs are held low independently of the other inputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
Obsolete Product(s) - ObsPIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
1/10
M74HCT174
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 5, 7, 10, 12, 15
3, 4, 6, 11, 13, 14
9
8 16
SYMBOL CLEAR
NAME AND FUNCTION
Asynchronous Master Reset (Active Low)
Q0 to Q5 Flip-Flop Outputs
D0 to D5
CLOCK GND Vcc
Data Inputs
Clock Input (LOW to HIGH, edge triggered) Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
CLEAR
t(s)L
H
ucH rodH
X : Don’t Care
te PLOGIC DIAGRAM
D X L H X
CK Q XL
L H Qn
FUNCTION...
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