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M88 Dataheets PDF



Part Number M88
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description In-System Programmable ISP Multiple-Memory/Logic
Datasheet M88 DatasheetM88 Datasheet (PDF)

M88 FAMILY In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems (with CPLD) for MCUs DATA BRIEFING s s Single Supply Voltage: – 5 V±10% for M88xxFxY – 3 V (+20/–10%) for M88xxFxW 1 or 2 Mbit of Primary Flash Memory (8 uniform sectors, 16K x 8, or 32K x 8) A second non-volatile memory: – 256 Kbit (32K x 8) EEPROM (for M8813F1x) or Flash memory (for M88x3F2x) – 4 uniform sectors (8K x 8) SRAM (16 Kbit, 2K x 8; or 64 Kbit, 8K x 8) Over 3,000 Gates of PLD: DPLD and CPLD 27 Reco.

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M88 FAMILY In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems (with CPLD) for MCUs DATA BRIEFING s s Single Supply Voltage: – 5 V±10% for M88xxFxY – 3 V (+20/–10%) for M88xxFxW 1 or 2 Mbit of Primary Flash Memory (8 uniform sectors, 16K x 8, or 32K x 8) A second non-volatile memory: – 256 Kbit (32K x 8) EEPROM (for M8813F1x) or Flash memory (for M88x3F2x) – 4 uniform sectors (8K x 8) SRAM (16 Kbit, 2K x 8; or 64 Kbit, 8K x 8) Over 3,000 Gates of PLD: DPLD and CPLD 27 Reconfigurable I/O ports Enhanced JTAG Serial Port Programmable power management Stand-by current: – 50 µA for M88xxFxY – 25 µA for M88xxFxW High Endurance: – 100,000 Erase/Write Cycles of Flash Memory – 10,000 Erase/Write Cycles of EEPROM – 1,000 Erase/Write Cycles of PLD PQFP52 (T) s s s s s s s s PLCC52 (K) Figure 1. Logic Diagram VCC DESCRIPTION The FLASH+PSD family of memory systems for microcontrollers (MCUs) brings In-SystemTable 1. Signal Names PA0-PA7 PB0-PB7 PC0-PC7 PC2 = Voltage Stand-by PD0-PD2 AD0-AD15 CNTL0-CNTL2 RESET VCC VSS Port-D Address/Data Control Reset Supply Voltage Ground Port-A Port-B Port-C 8 PA0-PA7 3 CNTL0CNTL2 16 AD0-AD15 3 RESET PD0-PD2 FLASH+PSD 8 PC0-PC7 8 PB0-PB7 VSS AI02856 June 2000 Complete data available on Data-on-Disc CD-ROM or at www.st.com 1/7 M88 FAMILY Figure 2A. PLCC Connections CNTL1 CNTL2 RESET CNTL0 PB0 PB1 PB2 PB3 PB4 PB5 GND PB6 PB7 Figure 2B. PQFP Connections 40 CNTLO PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 PC1 PC0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 46 45 44 43 42 41 40 39 38 37 36 35 34 27 28 29 31 32 30 33 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 VCC AD7 AD6 AD5 AD4 GND 19 AD3 26 PA7 14 PA6 15 PA5 16 PA4 17 PA3 18 PA2 20 PA1 21 PA0 22 AD0 23 AD1 24 AD2 25 PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 7 V CC 8 GND 9 PC3 10 PC2 11 PC1 12 PC0 13 39 AD15 38 AD14 37 AD13 36 AD12 35 AD11 34 AD10 33 AD9 32 AD8 31 V CC 30 AD7 29 AD6 28 AD5 27 AD4 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 AD1 AD2 GND AD0 AD3 AI02857 41 RESET 43 CNTL1 42 CNTL2 46 GND 52 PB0 51 PB1 50 PB2 49 PB3 48 PB4 47 PB5 45 PB6 44 PB7 4 Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. FLASH+PSD devices combine many of the peripheral functions found in MCU based applications. FLASH+PSD provides a glueless interface to most commonly-used ROMless MCUs. Table 2 summarizes all the devices in the M88 Family. The CPLD in the FLASH+PSD devices features an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal FLASH+PSD Table 2. Product Range1 Part Number M8813F1Y M8813F2Y M8834F2Y M8813F1W M8813F2W M8834F2W Primary Flash Memory 1 Mbit 1 Mbit 2 Mbit 1 Mbit 1 Mbit 2 Mbit Secondary NVM 256 Kbit EEPROM 256 Kbit Flash memory 256 Kbit Flash memory 256 Kbit EEPROM 256 Kbit Flash memory 256 Kbit Flash memory SRAM2 16 Kbit 16 Kbit 64 Kbit 16 Kbit 16 Kbit 64 Kbit I/O Ports Voltage Range 27 27 27 27 27 27 2.7-3.6 V 150 ns 4.5-5.5 V 90 ns or 150 ns Access Time Note: 1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management Unit (PMU), Automatic Power-down (APD) 2. SRAM may be backed up using an external battery. 7 5 3 2 52 51 50 49 48 47 6 1 AI02858 registers, to simplify communication between the MCU and other supporting devices. The FLASH+PSD device includes a JTAG Serial Programming interface, to allow In-System Programming (ISP) of the entire device. This feature reduces development time, simplifies the manufacturing flow, and dramatically lowers the cost of field upgrades. Using ST’s special FastJTAG programming, a design can be rapidly programmed into the FLASH+PSD. The innovative FLASH+PSD family solves key problems faced by designers when managing discrete Flash memory devices, such as: – Complex address decoding – In-System (first-time) Programming (ISP) – Concurrent EEPROM or Flash memory programming (IAP). 2/7 ADDRESS/DATA/CONTROL BUS PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM 8 SECTORS POWER MANGMT UNIT 1 OR 2 MBIT PRIMARY FLASH MEMORY 8 VSTDBY (PC2) CNTL0, CNTL1, CNTL2 SECTOR SELECTS FLASH DECODE PLD (DPLD) 73 SECTOR SELECTS SRAM SELECT PERIP I/O MODE SELECTS CSIOP RUNTIME CONTROL AND I/O REGISTERS 3 EXT CS TO PORT D 16 OUTPUT MACROCELLS PORT A ,B & C 24 INPUT MACROCELLS CLKIN PORT A ,B & C 16 OR 64 KBIT BATTERY BACKUP SRAM 256 KBIT SECONDARY EEPROM or FLASH MEMORY (BOOT OR DATA) 4 SECTORS Figure 3. FLASH+PSD Block Diagram PROG. MCU BUS INTRF. PROG. PORT PORT A PA0 – PA7 AD0 – AD15 ADIO PORT 73 FLASH ISP CPLD (CPLD) PROG. PORT PORT B PB0 – PB7 PROG. PORT MACROCELL FEEDBACK OR PORT INPUT CLKIN PORT C PC0 – PC7 GLOBAL CONFIG. & SECURITY PROG. PORT CLKIN (PD1) PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PORT D PD0 – PD2 .


M87C51FC M88 M88


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