In-System Programmable ISP Multiple-Memory and Logic
M89 FAMILY
In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems for MCUs
DATA BRIEFING
s
s
Single ...
Description
M89 FAMILY
In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems for MCUs
DATA BRIEFING
s
s
Single Supply Voltage: – 5 V±10% for M89xxFxY – 3 V (+20/–10%) for M89xxFxW 1 or 2 Mbit of Primary Flash Memory (8 uniform sectors, 16K x 8, or 32K x 8) A second non-volatile memory: – 256 Kbit (32K x 8) EEPROM (for M8913F1x) or Flash memory (for M89x3F2x) – 4 uniform sectors (8K x 8) SRAM (16 Kbit, 2K x 8; or 64 Kbit, 8K x 8) Over 2,000 Gates of PLD: DPLD and GPLD 27 Reconfigurable I/O ports Enhanced JTAG Serial Port Programmable power management Stand-by current: – 50 µA for M89xxFxY – 25 µA for M89xxFxW High Endurance: – 100,000 Erase/Write Cycles of Flash Memory – 10,000 Erase/Write Cycles of EEPROM – 1,000 Erase/Write Cycles of PLD
PQFP52 (T)
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s s s s s s
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PLCC52 (K)
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
PA0-PA7 PB0-PB7 PC0-PC7 PC2 = Voltage Stand-by PD0-PD2 AD0-AD15 CNTL0-CNTL2 RESET VCC VSS Port-D Address/Data Control Reset Supply Voltage Ground Port-A Port-B Port-C
8 PA0-PA7 3 CNTL0CNTL2 16 AD0-AD15 3 RESET PD0-PD2 FLASH+PSD 8 PC0-PC7 8 PB0-PB7
VSS
AI02856
June 2000
Complete data available on Data-on-Disc CD-ROM or at www.st.com
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M89 FAMILY
Figure 2A. PLCC Connections
CNTL1 CNTL2 RESET CNTL0 PB0 PB1 PB2 PB3 PB4 PB5 GND PB6 PB7
Figure 2B. PQFP Connections
40 CNTLO
PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 PC1 PC0
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
46 45 44 43 42 41 40 39 38 37 36 35 34 27 28 29 31 32 30 ...
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